📄 lpspi.lst
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15 ; Mask value for global int reg bit for TX instance
16 0000 SPIM_Radio_bINT_MASK: equ 04h
17 ; SPIM interrupt address
18 0000 SPIM_Radio_INT_REG: equ 0e1h
19
20 ; Do not use, this equate will be removed in a future release
21 0000 bSPIM_Radio_INT_MASK: equ 04h
22
23 ;--------------------------------------------------
24 ; Register constants and masks
25 ;--------------------------------------------------
26 0000 SPIM_Radio_SPIM_MODE_0: equ 00h ;MODE 0 - Leading edge latches data - pos clock
27 0000 SPIM_Radio_SPIM_MODE_1: equ 02h ;MODE 1 - Leading edge latches data - neg clock
28 0000 SPIM_Radio_SPIM_MODE_2: equ 04h ;MODE 2 - Trailing edge latches data - pos clock
29 0000 SPIM_Radio_SPIM_MODE_3: equ 06h ;MODE 3 - Trailing edge latches data - neg clock
30 0000 SPIM_Radio_SPIM_LSB_FIRST: equ 80h ;LSB bit transmitted/received first
31 0000 SPIM_Radio_SPIM_MSB_FIRST: equ 00h ;MSB bit transmitted/received first
32
33 ;---------------------------
34 ; SPI Status register masks
35 ;---------------------------
36 0000 SPIM_Radio_SPIM_RX_OVERRUN_ERROR: equ 40h ;Overrun error in received data
37 0000 SPIM_Radio_SPIM_TX_BUFFER_EMPTY: equ 10h ;TX Buffer register is ready for next data byte
38 0000 SPIM_Radio_SPIM_RX_BUFFER_FULL: equ 08h ;RX Buffer register has received current data
39 0000 SPIM_Radio_SPIM_SPI_COMPLETE: equ 20h ;SPI Tx/Rx cycle has completed
40
41 ;--------------------------------------------------
42 ; Registers used by SPIM_Radio
43 ;--------------------------------------------------
44 0000 SPIM_Radio_CONTROL_REG: equ 2bh ;Control register
45 0000 SPIM_Radio_SHIFT_REG: equ 28h ;TX Shift Register register
46 0000 SPIM_Radio_TX_BUFFER_REG: equ 29h ;TX Buffer Register
47 0000 SPIM_Radio_RX_BUFFER_REG: equ 2ah ;RX Buffer Register
48 0000 SPIM_Radio_FUNCTION_REG: equ 28h ;Function register
49 0000 SPIM_Radio_INPUT_REG: equ 29h ;Input register
50 0000 SPIM_Radio_OUTPUT_REG: equ 2ah ;Output register
1 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
2 ;
3 ; nLED1 address and mask equates
4 0000 nLED1_Data_ADDR: equ 0h
5 0000 nLED1_DriveMode_0_ADDR: equ 100h
6 0000 nLED1_DriveMode_1_ADDR: equ 101h
7 0000 nLED1_DriveMode_2_ADDR: equ 3h
8 0000 nLED1_GlobalSelect_ADDR: equ 2h
9 0000 nLED1_IntCtrl_0_ADDR: equ 102h
10 0000 nLED1_IntCtrl_1_ADDR: equ 103h
11 0000 nLED1_IntEn_ADDR: equ 1h
12 0000 nLED1_MASK: equ 20h
13 0000 nLED1_MUXBusCtrl_ADDR: equ 1d8h
14 ; nLED2 address and mask equates
15 0000 nLED2_Data_ADDR: equ 0h
16 0000 nLED2_DriveMode_0_ADDR: equ 100h
17 0000 nLED2_DriveMode_1_ADDR: equ 101h
18 0000 nLED2_DriveMode_2_ADDR: equ 3h
19 0000 nLED2_GlobalSelect_ADDR: equ 2h
20 0000 nLED2_IntCtrl_0_ADDR: equ 102h
21 0000 nLED2_IntCtrl_1_ADDR: equ 103h
22 0000 nLED2_IntEn_ADDR: equ 1h
23 0000 nLED2_MASK: equ 80h
24 0000 nLED2_MUXBusCtrl_ADDR: equ 1d8h
25 ; LP_nSS address and mask equates
26 0000 LP_nSS_Data_ADDR: equ 4h
27 0000 LP_nSS_DriveMode_0_ADDR: equ 104h
28 0000 LP_nSS_DriveMode_1_ADDR: equ 105h
29 0000 LP_nSS_DriveMode_2_ADDR: equ 7h
30 0000 LP_nSS_GlobalSelect_ADDR: equ 6h
31 0000 LP_nSS_IntCtrl_0_ADDR: equ 106h
32 0000 LP_nSS_IntCtrl_1_ADDR: equ 107h
33 0000 LP_nSS_IntEn_ADDR: equ 5h
34 0000 LP_nSS_MASK: equ 4h
35 0000 LP_nSS_MUXBusCtrl_ADDR: equ 1d9h
36 ; LP_IRQ address and mask equates
37 0000 LP_IRQ_Data_ADDR: equ 4h
38 0000 LP_IRQ_DriveMode_0_ADDR: equ 104h
39 0000 LP_IRQ_DriveMode_1_ADDR: equ 105h
40 0000 LP_IRQ_DriveMode_2_ADDR: equ 7h
41 0000 LP_IRQ_GlobalSelect_ADDR: equ 6h
42 0000 LP_IRQ_IntCtrl_0_ADDR: equ 106h
43 0000 LP_IRQ_IntCtrl_1_ADDR: equ 107h
44 0000 LP_IRQ_IntEn_ADDR: equ 5h
45 0000 LP_IRQ_MASK: equ 8h
46 0000 LP_IRQ_MUXBusCtrl_ADDR: equ 1d9h
47 ; SCK address and mask equates
48 0000 SCK_Data_ADDR: equ 4h
49 0000 SCK_DriveMode_0_ADDR: equ 104h
50 0000 SCK_DriveMode_1_ADDR: equ 105h
51 0000 SCK_DriveMode_2_ADDR: equ 7h
52 0000 SCK_GlobalSelect_ADDR: equ 6h
53 0000 SCK_IntCtrl_0_ADDR: equ 106h
54 0000 SCK_IntCtrl_1_ADDR: equ 107h
55 0000 SCK_IntEn_ADDR: equ 5h
56 0000 SCK_MASK: equ 10h
57 0000 SCK_MUXBusCtrl_ADDR: equ 1d9h
58 ; MISO address and mask equates
59 0000 MISO_Data_ADDR: equ 4h
60 0000 MISO_DriveMode_0_ADDR: equ 104h
61 0000 MISO_DriveMode_1_ADDR: equ 105h
62 0000 MISO_DriveMode_2_ADDR: equ 7h
63 0000 MISO_GlobalSelect_ADDR: equ 6h
64 0000 MISO_IntCtrl_0_ADDR: equ 106h
65 0000 MISO_IntCtrl_1_ADDR: equ 107h
66 0000 MISO_IntEn_ADDR: equ 5h
67 0000 MISO_MASK: equ 20h
68 0000 MISO_MUXBusCtrl_ADDR: equ 1d9h
69 ; MOSI address and mask equates
70 0000 MOSI_Data_ADDR: equ 4h
71 0000 MOSI_DriveMode_0_ADDR: equ 104h
72 0000 MOSI_DriveMode_1_ADDR: equ 105h
73 0000 MOSI_DriveMode_2_ADDR: equ 7h
74 0000 MOSI_GlobalSelect_ADDR: equ 6h
75 0000 MOSI_IntCtrl_0_ADDR: equ 106h
76 0000 MOSI_IntCtrl_1_ADDR: equ 107h
77 0000 MOSI_IntEn_ADDR: equ 5h
78 0000 MOSI_MASK: equ 80h
79 0000 MOSI_MUXBusCtrl_ADDR: equ 1d9h
80 ; RST address and mask equates
81 0000 RST_Data_ADDR: equ 8h
82 0000 RST_DriveMode_0_ADDR: equ 108h
83 0000 RST_DriveMode_1_ADDR: equ 109h
84 0000 RST_DriveMode_2_ADDR: equ bh
85 0000 RST_GlobalSelect_ADDR: equ ah
86 0000 RST_IntCtrl_0_ADDR: equ 10ah
87 0000 RST_IntCtrl_1_ADDR: equ 10bh
88 0000 RST_IntEn_ADDR: equ 9h
89 0000 RST_MASK: equ 20h
90 0000 RST_MUXBusCtrl_ADDR: equ 1dah
1 ;--------------------------------------------------------------------------
2 ;
3 ; Filename: lpRegs.inc
4 ;
5 ; Description: Defines CYRF6936 registers
6 ;
7 ;--------------------------------------------------------------------------
8 ; WirelessUSB LP Radio Driver Version 1.1
9 ;--------------------------------------------------------------------------
10 ;
11 ; Copyright 2005-2006, Cypress Semiconductor Corporation.
12 ;
13 ; This software is owned by Cypress Semiconductor Corporation (Cypress)
14 ; and is protected by and subject to worldwide patent protection (United
15 ; States and foreign), United States copyright laws and international
16 ; treaty provisions. Cypress hereby grants to licensee a personal,
17 ; non-exclusive, non-transferable license to copy, use, modify, create
18 ; derivative works of, and compile the Cypress Source Code and derivative
19 ; works for the sole purpose of creating custom software in support of
20 ; licensee product to be used only in conjunction with a Cypress integrated
21 ; circuit as specified in the applicable agreement. Any reproduction,
22 ; modification, translation, compilation, or representation of this
23 ; software except as specified above is prohibited without the express
24 ; written permission of Cypress.
25 ;
26 ; Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
27 ; WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 ; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
29 ; Cypress reserves the right to make changes without further notice to the
30 ; materials described herein. Cypress does not assume any liability arising
31 ; out of the application or use of any product or circuit described herein.
32 ; Cypress does not authorize its products for use as critical components in
33 ; life-support systems where a malfunction or failure may reasonably be
34 ; expected to result in significant injury to the user. The inclusion of
35 ; Cypress' product in a life-support systems application implies that the
36 ; manufacturer assumes all risk of such use and in doing so indemnifies
37 ; Cypress against all charges.
38 ;
39 ; Use may be limited by and subject to the applicable Cypress software
40 ; license agreement.
41 ;
42 ;--------------------------------------------------------------------------
43
44
45 ; -------------------------------
46 ; Channel register
47 ; -------------------------------
48 0000 CHANNEL_ADR: equ 0x00
49 0000 CHANNEL_RST: equ 0x48
50 0000 CHANNEL_MSK: equ 0x7f
51
52 0000 CHANNEL_MAX: equ 0x62
53 0000 CHANNEL_MIN: equ 0x00
54 0000 CHANNEL_2P498_GHZ: equ 0x62
55 0000 CHANNEL_2P4_GHZ: equ 0x00
56
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