📄 lpnonstreaming.lst
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239 0000 XS_IRQ_EN: equ 0x20
240 0000 XOUT_FREQ_MSK: equ 0x07
241
242 ; XOUT_FNC values
243 0000 XOUT_FNC_XOUT_FREQ: equ 0x00
244 0000 XOUT_FNC_PA_N: equ 0x40
245 0000 XOUT_FNC_RAD_STREAM: equ 0x80
246 0000 XOUT_FNC_GPIO: equ 0xC0
247
248 ; XOUT_FREQ values
249 0000 XOUT_FREQ_12MHZ: equ 0x00
250 0000 XOUT_FREQ_6MHZ: equ 0x01
251 0000 XOUT_FREQ_3MHZ: equ 0x02
252 0000 XOUT_FREQ_1P5MHZ: equ 0x03
253 0000 XOUT_FREQ_P75MHZ: equ 0x04
254
255
256 ; -------------------------------
257 ; I/O Configuration register
258 ; -------------------------------
259 0000 IO_CFG_ADR: equ 0x0d
260 0000 IO_CFG_RST: equ 0x00
261 0000 IO_CFG_MSK: equ 0xff
262
263 ; single flag bits & multi-bit-field masks
264 0000 IRQ_OD: equ 0x80
265 0000 IRQ_POL: equ 0x40
266 0000 MISO_OD: equ 0x20
267 0000 XOUT_OD: equ 0x10
268 0000 PACTL_OD: equ 0x08
269 0000 PACTL_GPIO: equ 0x04
270 0000 SPI_3_PIN: equ 0x02
271 0000 IRQ_GPIO: equ 0x01
272
273
274 ; -------------------------------
275 ; GPIO Control register
276 ; -------------------------------
277 0000 GPIO_CTRL_ADR: equ 0x0e
278 0000 GPIO_CTRL_RST: equ 0x00
279 0000 GPIO_CTRL_MSK: equ 0xf0
280
281 ; single flag bits & multi-bit-field masks
282 0000 XOUT_OP: equ 0x80
283 0000 MISO_OP: equ 0x40
284 0000 PACTL_OP: equ 0x20
285 0000 IRQ_OP: equ 0x10
286 0000 XOUT_IP: equ 0x08
287 0000 MISO_IP: equ 0x04
288 0000 PACTL_IP: equ 0x02
289 0000 IRQ_IP: equ 0x01
290
291
292 ; -------------------------------
293 ; Transaction Configuration register
294 ; -------------------------------
295 0000 XACT_CFG_ADR: equ 0x0f
296 0000 XACT_CFG_RST: equ 0x80
297
298 ; single flag bits & multi-bit-field masks
299 0000 ACK_EN: equ 0x80
300 0000 FRC_END_STATE: equ 0x20
301 0000 END_STATE_MSK: equ 0x1c
302 0000 ACK_TO_MSK: equ 0x03
303
304 ; END_STATE field values
305 0000 END_STATE_SLEEP: equ 0x00
306 0000 END_STATE_IDLE: equ 0x04
307 0000 END_STATE_TXSYNTH: equ 0x08
308 0000 END_STATE_RXSYNTH: equ 0x0C
309 0000 END_STATE_RX: equ 0x10
310
311 ; ACK_TO field values
312 0000 ACK_TO_4X: equ 0x00
313 0000 ACK_TO_8X: equ 0x01
314 0000 ACK_TO_12X: equ 0x02
315 0000 ACK_TO_15X: equ 0x03
316
317
318 ; -------------------------------
319 ; Framing Configuration register
320 ; -------------------------------
321 0000 FRAMING_CFG_ADR: equ 0x10
322 0000 FRAMING_CFG_RST: equ 0xa5
323
324 ; single flag bits & multi-bit-field masks
325 0000 SOP_EN: equ 0x80
326 0000 SOP_LEN: equ 0x40
327 0000 LEN_EN: equ 0x20
328 0000 SOP_THRESH_MSK: equ 0x1f
329
330
331 ; -------------------------------
332 ; Data Threshold 32 register
333 ; -------------------------------
334 0000 DATA32_THOLD_ADR: equ 0x11
335 0000 DAT32_THRESH_RST: equ 0x04
336 0000 DAT32_THRESH_MSK: equ 0x0f
337
338
339 ; -------------------------------
340 ; Data Threshold 64 register
341 ; -------------------------------
342 0000 DATA64_THOLD_ADR: equ 0x12
343 0000 DAT64_THRESH_RST: equ 0x0a
344 0000 DAT64_THRESH_MSK: equ 0x1f
345
346
347 ; -------------------------------
348 ; RSSI register
349 ; -------------------------------
350 0000 RSSI_ADR: equ 0x13
351 0000 RSSI_RST: equ 0x20
352
353 ; single flag bits & multi-bit-field masks
354 0000 SOP_RSSI: equ 0x80
355 0000 LNA_STATE: equ 0x20
356 0000 RSSI_LVL_MSK: equ 0x1f
357
358
359 ; -------------------------------
360 ; EOP Control register
361 ; -------------------------------
362 0000 EOP_CTRL_ADR: equ 0x14
363 0000 EOP_CTRL_RST: equ 0xa4
364
365 ; single flag bits & multi-bit-field masks
366 0000 HINT_EN: equ 0x80
367 0000 HINT_EOP_MSK: equ 0x70
368 0000 EOP_MSK: equ 0x0f
369
370
371 ; -------------------------------
372 ; CRC Seed registers
373 ; -------------------------------
374 0000 CRC_SEED_LSB_ADR: equ 0x15
375 0000 CRC_SEED_MSB_ADR: equ 0x16
376 0000 CRC_SEED_LSB_RST: equ 0x00
377 0000 CRC_SEED_MSB_RST: equ 0x00
378
379 ; CRC related values
380 ; USB CRC-16
381 0000 CRC_POLY_MSB: equ 0x80
382 0000 CRC_POLY_LSB: equ 0x05
383 0000 CRC_RESI_MSB: equ 0x80
384 0000 CRC_RESI_LSB: equ 0x0d
385
386
387 ; -------------------------------
388 ; TX CRC Calculated registers
389 ; -------------------------------
390 0000 TX_CRC_LSB_ADR: equ 0x17
391 0000 TX_CRC_MSB_ADR: equ 0x18
392
393
394 ; -------------------------------
395 ; RX CRC Field registers
396 ; -------------------------------
397 0000 RX_CRC_LSB_ADR: equ 0x19
398 0000 RX_CRC_MSB_ADR: equ 0x1a
399 0000 RX_CRC_LSB_RST: equ 0xff
400 0000 RX_CRC_MSB_RST: equ 0xff
401
402
403 ; -------------------------------
404 ; Synth Offset registers
405 ; -------------------------------
406 0000 TX_OFFSET_LSB_ADR: equ 0x1b
407 0000 TX_OFFSET_MSB_ADR: equ 0x1c
408 0000 TX_OFFSET_LSB_RST: equ 0x00
409 0000 TX_OFFSET_MSB_RST: equ 0x00
410
411 ; single flag bits & multi-bit-field masks
412 0000 STRIM_MSB_MSK: equ 0x0f
413 0000 STRIM_LSB_MSK: equ 0xff
414
415
416 ; -------------------------------
417 ; Mode Override register
418 ; -------------------------------
419 0000 MODE_OVERRIDE_ADR: equ 0x1d
420 0000 MODE_OVERRIDE_RST: equ 0x00
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