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HI-TECH Software Macro Assembler (PSoC MCU) V9.60PL4
Thu Jul 17 10:42:59 2008
1 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
2 ;
3 ;=============================================================================
4 ; FILENAME: GlobalParams.inc
5 ; DATE: 27 September 2004
6 ;
7 ; DESCRIPTION:
8 ; Constants describing many of the global parameter settings.
9 ; This file contains equates to support oscillator register initialization
10 ; for the CY7C64215-28PVXC
11 ;
12 ; Copyright (C) Cypress MicroSystems 2000-2004. All rights reserved.
13 ;
14 ; NOTES:
15 ; Do not modify this file. It is generated by PSoC Designer each time the
16 ; generate application function is run. The values of the parameters in this
17 ; file can be modified by changing the values of the global parameters in the
18 ; device editor.
19 ;=============================================================================
20 ;
21
22 0000 CPU_CLOCK: equ 3h ;CPU clock value
23 0000 CPU_CLOCK_MASK: equ 7h ;CPU clock mask
24 0000 CPU_CLOCK_JUST: equ 3h ;CPU clock value justified
25 0000 SLEEP_TIMER: equ 0h ;Sleep Timer value
26 0000 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
27 0000 SLEEP_TIMER_JUST: equ 0h ;Sleep Timer value justified
28 0000 LVD_TBEN: equ 0 ; Low Voltage Throttle-back enable value
29 0000 LVD_TBEN_MASK: equ 8 ; Low Voltage Throttle-back enable mask
30 0000 LVD_TBEN_JUST: equ 0 ; Low Voltage Throttle-back enable justified
31 0000 TRIP_VOLTAGE: equ 7h ;Trip Voltage value
32 0000 TRIP_VOLTAGE_MASK: equ 7h ;Trip Voltage mask
33 0000 TRIP_VOLTAGE_JUST: equ 7h ;Trip Voltage justified
34
35 0000 POWER_SETTING: equ 10h
36 0000 POWER_SET_5V0: equ 10h ; MASK for 5.0V operation, fast and slow
37 0000 POWER_SET_5V0_24MHZ: equ 10h ; Power Setting value for 5.0V fast
38 0000 POWER_SET_3V3: equ 08h ; MASK for 3.3V operation, fast and slow
39 0000 POWER_SET_3V3_24MHZ: equ 08h ; Power Setting value for 3.3V fast
40
41 0000 COMM_RX_PRESENT: equ 1 ;1 = TRUE
42 0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
43
44 0000 CLOCK_DIV_VC1: equ 5h ;VC1 clock divider
45 0000 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
46 0000 CLOCK_DIV_VC1_JUST: equ 50h ;VC1 clock divider justified
47 0000 CLOCK_DIV_VC2: equ 5h ;VC2 clock divider
48 0000 CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
49 0000 CLOCK_DIV_VC2_JUST: equ 5h ;VC2 clock divider justified
50 0000 CLOCK_INPUT_VC3: equ 0h ;VC3 clock source
51 0000 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
52 0000 CLOCK_INPUT_VC3_JUST: equ 0h ;VC3 clock source justified
53 0000 CLOCK_DIV_VC3: equ 13h ;VC3 clock divider
54 0000 CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
55 0000 CLOCK_DIV_VC3_JUST: equ 13h ;VC3 clock divider justified
56 0000 ANALOG_BUFFER_PWR: equ 0h ;Analog buffer power level
57 0000 ANALOG_BUFFER_PWR_MASK: equ 1h ;Analog buffer power level mask
58 0000 ANALOG_BUFFER_PWR_JUST: equ 0h ;Analog buffer power level justified
59 0000 ANALOG_POWER: equ 5h ;Analog power control
60 0000 ANALOG_POWER_MASK: equ 7h ;Analog power control mask
61 0000 ANALOG_POWER_JUST: equ 5h ;Analog power control justified
62 0000 OP_AMP_BIAS: equ 0h ;Op amp bias level
63 0000 OP_AMP_BIAS_MASK: equ 40h ;Op amp bias level mask
64 0000 OP_AMP_BIAS_JUST: equ 0h ;Op amp bias level justified
65 0000 REF_MUX: equ 0h ;Ref mux setting
66 0000 REF_MUX_MASK: equ 38h ;Ref mux setting mask
67 0000 REF_MUX_JUST: equ 0h ;Ref mux setting justified
68 0000 AGND_BYPASS: equ 0h ;AGndBypass setting
69 0000 AGND_BYPASS_MASK: equ 40h ;AGndBypass setting mask
70 0000 AGND_BYPASS_JUST: equ 0h ;AGndBypass setting justified
71 0000 SYSCLK_SOURCE: equ (0h | 0h) ;SysClk Source setting
72 0000 SYSCLK_SOURCE_MASK: equ (4h | 2h) ;SysClk Source setting mask
73 0000 SYSCLK_SOURCE_JUST: equ (0h | 0h) ;SysClk Source setting justified
74 0000 SYSCLK_2_DISABLE: equ 0h ;SysClk*2 Disable setting
75 0000 SYSCLK_2_DISABLE_MASK: equ 1h ;SysClk*2 Disable setting mask
76 0000 SYSCLK_2_DISABLE_JUST: equ 0h ;SysClk*2 Disable setting justified
77 ;
78 ; register initial values
79 ;
80 0000 ANALOG_IO_CONTROL: equ 0h ;Analog IO Control register (ABF_CR)
81 0000 PORT_0_GLOBAL_SELECT: equ 0h ;Port 0 global select register (PRT0GS)
82 0000 PORT_0_DRIVE_0: equ 0h ;Port 0 drive mode 0 register (PRT0DM0)
83 0000 PORT_0_DRIVE_1: equ ffh ;Port 0 drive mode 1 register (PRT0DM1)
84 0000 PORT_0_DRIVE_2: equ ffh ;Port 0 drive mode 2 register (PRT0DM2)
85 0000 PORT_0_INTENABLE: equ 0h ;Port 0 interrupt enable register (PRT0IE)
86 0000 PORT_0_INTCTRL_0: equ 0h ;Port 0 interrupt control 0 register (PRT0IC0)
87 0000 PORT_0_INTCTRL_1: equ 0h ;Port 0 interrupt control 1 register (PRT0IC1)
88 0000 PORT_1_GLOBAL_SELECT: equ b0h ;Port 1 global select register (PRT1GS)
89 0000 PORT_1_DRIVE_0: equ 90h ;Port 1 drive mode 0 register (PRT1DM0)
90 0000 PORT_1_DRIVE_1: equ 6fh ;Port 1 drive mode 1 register (PRT1DM1)
91 0000 PORT_1_DRIVE_2: equ 4fh ;Port 1 drive mode 2 register (PRT1DM2)
92 0000 PORT_1_INTENABLE: equ 0h ;Port 1 interrupt enable register (PRT1IE)
93 0000 PORT_1_INTCTRL_0: equ 0h ;Port 1 interrupt control 0 register (PRT1IC0)
94 0000 PORT_1_INTCTRL_1: equ 0h ;Port 1 interrupt control 1 register (PRT1IC1)
95 0000 PORT_2_GLOBAL_SELECT: equ 0h ;Port 2 global select register (PRT2GS)
96 0000 PORT_2_DRIVE_0: equ 0h ;Port 2 drive mode 0 register (PRT2DM0)
97 0000 PORT_2_DRIVE_1: equ 3fh ;Port 2 drive mode 1 register (PRT2DM1)
98 0000 PORT_2_DRIVE_2: equ 3fh ;Port 2 drive mode 2 register (PRT2DM2)
99 0000 PORT_2_INTENABLE: equ 0h ;Port 2 interrupt enable register (PRT2IE)
100 0000 PORT_2_INTCTRL_0: equ 0h ;Port 2 interrupt control 0 register (PRT2IC0)
101 0000 PORT_2_INTCTRL_1: equ 0h ;Port 2 interrupt control 1 register (PRT2IC1)
102 0000 PORT_3_GLOBAL_SELECT: equ 0h ;Port 3 global select register (PRT3GS)
103 0000 PORT_3_DRIVE_0: equ 0h ;Port 3 drive mode 0 register (PRT3DM0)
104 0000 PORT_3_DRIVE_1: equ 0h ;Port 3 drive mode 1 register (PRT3DM1)
105 0000 PORT_3_DRIVE_2: equ 0h ;Port 3 drive mode 2 register (PRT3DM2)
106 0000 PORT_3_INTENABLE: equ 0h ;Port 3 interrupt enable register (PRT3IE)
107 0000 PORT_3_INTCTRL_0: equ 0h ;Port 3 interrupt control 0 register (PRT3IC0)
108 0000 PORT_3_INTCTRL_1: equ 0h ;Port 3 interrupt control 1 register (PRT3IC1)
109 0000 PORT_4_GLOBAL_SELECT: equ 0h ;Port 4 global select register (PRT4GS)
110 0000 PORT_4_DRIVE_0: equ 0h ;Port 4 drive mode 0 register (PRT4DM0)
111 0000 PORT_4_DRIVE_1: equ 0h ;Port 4 drive mode 1 register (PRT4DM1)
112 0000 PORT_4_DRIVE_2: equ 0h ;Port 4 drive mode 2 register (PRT4DM2)
113 0000 PORT_4_INTENABLE: equ 0h ;Port 4 interrupt enable register (PRT4IE)
114 0000 PORT_4_INTCTRL_0: equ 0h ;Port 4 interrupt control 0 register (PRT4IC0)
115 0000 PORT_4_INTCTRL_1: equ 0h ;Port 4 interrupt control 1 register (PRT4IC1)
116 0000 PORT_5_GLOBAL_SELECT: equ 0h ;Port 5 global select register (PRT5GS)
117 0000 PORT_5_DRIVE_0: equ 0h ;Port 5 drive mode 0 register (PRT5DM0)
118 0000 PORT_5_DRIVE_1: equ 0h ;Port 5 drive mode 1 register (PRT5DM1)
119 0000 PORT_5_DRIVE_2: equ 0h ;Port 5 drive mode 2 register (PRT5DM2)
120 0000 PORT_5_INTENABLE: equ 0h ;Port 5 interrupt enable register (PRT5IE)
121 0000 PORT_5_INTCTRL_0: equ 0h ;Port 5 interrupt control 0 register (PRT5IC0)
122 0000 PORT_5_INTCTRL_1: equ 0h ;Port 5 interrupt control 1 register (PRT5IC1)
123 0000 PORT_7_GLOBAL_SELECT: equ 0h ;Port 7 global select register (PRT7GS)
124 0000 PORT_7_DRIVE_0: equ 0h ;Port 7 drive mode 0 register (PRT7DM0)
125 0000 PORT_7_DRIVE_1: equ 0h ;Port 7 drive mode 1 register (PRT7DM1)
126 0000 PORT_7_DRIVE_2: equ 0h ;Port 7 drive mode 2 register (PRT7DM2)
127 0000 PORT_7_INTENABLE: equ 0h ;Port 7 interrupt enable register (PRT7IE)
128 0000 PORT_7_INTCTRL_0: equ 0h ;Port 7 interrupt control 0 register (PRT7IC0)
129 0000 PORT_7_INTCTRL_1: equ 0h ;Port 7 interrupt control 1 register (PRT7IC1)
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- CY7C64215 Microcontroller Device System Declarations
4 ;;;
5 ;;; Copyright (c) 2005 Cypress Semiconductor, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress CY7C64215 Microcontroller.
10 ;;;
11 ;;; Last Modified: August 31, 2005
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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