📄 lpnonstreaming.lis
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0020 nLED1_MASK: equ 20h
01D8 nLED1_MUXBusCtrl_ADDR: equ 1d8h
0000 ; nLED2 address and mask equates
0000 nLED2_Data_ADDR: equ 0h
0100 nLED2_DriveMode_0_ADDR: equ 100h
0101 nLED2_DriveMode_1_ADDR: equ 101h
0003 nLED2_DriveMode_2_ADDR: equ 3h
0002 nLED2_GlobalSelect_ADDR: equ 2h
0102 nLED2_IntCtrl_0_ADDR: equ 102h
0103 nLED2_IntCtrl_1_ADDR: equ 103h
0001 nLED2_IntEn_ADDR: equ 1h
0080 nLED2_MASK: equ 80h
01D8 nLED2_MUXBusCtrl_ADDR: equ 1d8h
0000 ; LP_nSS address and mask equates
0004 LP_nSS_Data_ADDR: equ 4h
0104 LP_nSS_DriveMode_0_ADDR: equ 104h
0105 LP_nSS_DriveMode_1_ADDR: equ 105h
0007 LP_nSS_DriveMode_2_ADDR: equ 7h
0006 LP_nSS_GlobalSelect_ADDR: equ 6h
0106 LP_nSS_IntCtrl_0_ADDR: equ 106h
0107 LP_nSS_IntCtrl_1_ADDR: equ 107h
0005 LP_nSS_IntEn_ADDR: equ 5h
0004 LP_nSS_MASK: equ 4h
01D9 LP_nSS_MUXBusCtrl_ADDR: equ 1d9h
0000 ; LP_IRQ address and mask equates
0004 LP_IRQ_Data_ADDR: equ 4h
0104 LP_IRQ_DriveMode_0_ADDR: equ 104h
0105 LP_IRQ_DriveMode_1_ADDR: equ 105h
0007 LP_IRQ_DriveMode_2_ADDR: equ 7h
0006 LP_IRQ_GlobalSelect_ADDR: equ 6h
0106 LP_IRQ_IntCtrl_0_ADDR: equ 106h
0107 LP_IRQ_IntCtrl_1_ADDR: equ 107h
0005 LP_IRQ_IntEn_ADDR: equ 5h
0008 LP_IRQ_MASK: equ 8h
01D9 LP_IRQ_MUXBusCtrl_ADDR: equ 1d9h
0000 ; SCK address and mask equates
0004 SCK_Data_ADDR: equ 4h
0104 SCK_DriveMode_0_ADDR: equ 104h
0105 SCK_DriveMode_1_ADDR: equ 105h
0007 SCK_DriveMode_2_ADDR: equ 7h
0006 SCK_GlobalSelect_ADDR: equ 6h
0106 SCK_IntCtrl_0_ADDR: equ 106h
0107 SCK_IntCtrl_1_ADDR: equ 107h
0005 SCK_IntEn_ADDR: equ 5h
0010 SCK_MASK: equ 10h
01D9 SCK_MUXBusCtrl_ADDR: equ 1d9h
0000 ; MISO address and mask equates
0004 MISO_Data_ADDR: equ 4h
0104 MISO_DriveMode_0_ADDR: equ 104h
0105 MISO_DriveMode_1_ADDR: equ 105h
0007 MISO_DriveMode_2_ADDR: equ 7h
0006 MISO_GlobalSelect_ADDR: equ 6h
0106 MISO_IntCtrl_0_ADDR: equ 106h
0107 MISO_IntCtrl_1_ADDR: equ 107h
0005 MISO_IntEn_ADDR: equ 5h
0020 MISO_MASK: equ 20h
01D9 MISO_MUXBusCtrl_ADDR: equ 1d9h
0000 ; MOSI address and mask equates
0004 MOSI_Data_ADDR: equ 4h
0104 MOSI_DriveMode_0_ADDR: equ 104h
0105 MOSI_DriveMode_1_ADDR: equ 105h
0007 MOSI_DriveMode_2_ADDR: equ 7h
0006 MOSI_GlobalSelect_ADDR: equ 6h
0106 MOSI_IntCtrl_0_ADDR: equ 106h
0107 MOSI_IntCtrl_1_ADDR: equ 107h
0005 MOSI_IntEn_ADDR: equ 5h
0080 MOSI_MASK: equ 80h
01D9 MOSI_MUXBusCtrl_ADDR: equ 1d9h
0000 ; RST address and mask equates
0008 RST_Data_ADDR: equ 8h
0108 RST_DriveMode_0_ADDR: equ 108h
0109 RST_DriveMode_1_ADDR: equ 109h
000B RST_DriveMode_2_ADDR: equ bh
000A RST_GlobalSelect_ADDR: equ ah
010A RST_IntCtrl_0_ADDR: equ 10ah
010B RST_IntCtrl_1_ADDR: equ 10bh
0009 RST_IntEn_ADDR: equ 9h
0020 RST_MASK: equ 20h
01DA RST_MUXBusCtrl_ADDR: equ 1dah
0000 CHANNEL_ADR: equ 0x00
0048 CHANNEL_RST: equ 0x48
007F CHANNEL_MSK: equ 0x7f
0000
0062 CHANNEL_MAX: equ 0x62
0000 CHANNEL_MIN: equ 0x00
0062 CHANNEL_2P498_GHZ: equ 0x62
0000 CHANNEL_2P4_GHZ: equ 0x00
0000
0000
0000 ; -------------------------------
0000 ; TX Length register
0000 ; -------------------------------
0001 TX_LENGTH_ADR: equ 0x01
0000 TX_LENGTH_RST: equ 0x00
00FF TX_LENGTH_MSK: equ 0xff
0000
0000
0000 ; -------------------------------
0000 ; TX Control register
0000 ; -------------------------------
0002 TX_CTRL_ADR: equ 0x02
0003 TX_CTRL_RST: equ 0x03
0000
0000 ; See TX_IRQ for remaining bit position definitions
0000
0000 ; TX_CTRL bit masks
0080 TX_GO: equ 0x80
0040 TX_CLR: equ 0x40
0000
0000
0000 ; -------------------------------
0000 ; TX Configuration register
0000 ; -------------------------------
0003 TX_CFG_ADR: equ 0x03
0005 TX_CFG_RST: equ 0x05
0000
0000 ; separate bit field masks
0020 TX_DATCODE_LEN_MSK: equ 0x20
0018 TX_DATMODE_MSK: equ 0x18
0007 PA_VAL_MSK: equ 0x07
0000
0000 ; DATCODE_LEN register masks
0020 DATCODE_LEN_64: equ 0x20
0000 DATCODE_LEN_32: equ 0x00
0000
0000 ; DATMODE register masks
0000 DATMODE_1MBPS: equ 0x00
0008 DATMODE_8DR: equ 0x08
0010 DATMODE_DDR: equ 0x10
0018 DATMODE_SDR: equ 0x18
0000
0000 ; PA_SET register masks
0000 PA_N30_DBM: equ 0x00
0001 PA_N25_DBM: equ 0x01
0002 PA_N20_DBM: equ 0x02
0003 PA_N15_DBM: equ 0x03
0004 PA_N10_DBM: equ 0x04
0005 PA_N5_DBM: equ 0x05
0006 PA_0_DBM: equ 0x06
0007 PA_4_DBM: equ 0x07
0000
0000
0000 ; -------------------------------
0000 ; TX IRQ Status register
0000 ; -------------------------------
0004 TX_IRQ_STATUS_ADR: equ 0x04
0000
0000 ; TX_IRQ bit masks
0080 XS_IRQ: equ 0x80
0040 LV_IRQ: equ 0x40
0020 TXB15_IRQ: equ 0x20
0010 TXB8_IRQ: equ 0x10
0008 TXB0_IRQ: equ 0x08
0004 TXBERR_IRQ: equ 0x04
0002 TXC_IRQ: equ 0x02
0001 TXE_IRQ: equ 0x01
0000
0000
0000 ; -------------------------------
0000 ; RX Control register
0000 ; -------------------------------
0005 RX_CTRL_ADR: equ 0x05
0007 RX_CTRL_RST: equ 0x07
0000
0000 ; See RX_IRQ register for bit positions definitions also used for this register
0000
0000 ; RX_CTRL bit masks
0080 RX_GO: equ 0x80
0000
0000
0000 ; -------------------------------
0000 ; RX Configuration register
0000 ; -------------------------------
0006 RX_CFG_ADR: equ 0x06
0092 RX_CFG_RST: equ 0x92
0000
0080 AUTO_AGC_EN: equ 0x80
0040 LNA_EN: equ 0x40
0020 ATT_EN: equ 0x20
0010 HI: equ 0x10
0000 LO: equ 0x00
0008 FASTTURN_EN: equ 0x08
0002 RXOW_EN: equ 0x02
0001 VLD_EN: equ 0x01
0000
0000
0000 ; -------------------------------
0000 ; RX IRQ register
0000 ; -------------------------------
0007 RX_IRQ_STATUS_ADR: equ 0x07
0000 ; There is no default value for this register.
0000
0000 ; RX_IRQ bit masks
0080 RXOW_IRQ: equ 0x80
0040 SOFDET_IRQ: equ 0x40
0020 RXB16_IRQ: equ 0x20
0010 RXB8_IRQ: equ 0x10
0008 RXB1_IRQ: equ 0x08
0004 RXBERR_IRQ: equ 0x04
0002 RXC_IRQ: equ 0x02
0001 RXE_IRQ: equ 0x01
0000
0000
0000 ; -------------------------------
0000 ; RX Status register
0000 ; -------------------------------
0008 RX_STATUS_ADR: equ 0x08
0000 // There is no default value for this register.
0000
0000 ; single flag bits & multi-bit-field masks
0080 RX_ACK: equ 0x80
0040 RX_PKTERR: equ 0x40
0020 RX_EOPERR: equ 0x20
0010 RX_CRC0: equ 0x10
0008 RX_BAD_CRC: equ 0x08
0004 RX_DATCODE_LEN: equ 0x04
0003 RX_DATMODE_MSK: equ 0x03
0000
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