📄 psocconfig.lst
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289
290 ; Switched Cap PSoC blockType C Row 1 Col 0
291 0000 ASC10CR0: equ 80h ; Control register 0 (RW)
292 0000 ASC10CR1: equ 81h ; Control register 1 (RW)
293 0000 ASC10CR2: equ 82h ; Control register 2 (RW)
294 0000 ASC10CR3: equ 83h ; Control register 3 (RW)
295
296 ; Switched Cap PSoC blockType D Row 1 Col 1
297 0000 ASD11CR0: equ 84h ; Control register 0 (RW)
298 0000 ASD11CR1: equ 85h ; Control register 1 (RW)
299 0000 ASD11CR2: equ 86h ; Control register 2 (RW)
300 0000 ASD11CR3: equ 87h ; Control register 3 (RW)
301
302 ; Switched Cap PSoC blockType D Row 2 Col 0
303 0000 ASD20CR0: equ 90h ; Control register 0 (RW)
304 0000 ASD20CR1: equ 91h ; Control register 1 (RW)
305 0000 ASD20CR2: equ 92h ; Control register 2 (RW)
306 0000 ASD20CR3: equ 93h ; Control register 3 (RW)
307
308 ; Switched Cap PSoC blockType C Row 2 Col 1
309 0000 ASC21CR0: equ 94h ; Control register 0 (RW)
310 0000 ASC21CR1: equ 95h ; Control register 1 (RW)
311 0000 ASC21CR2: equ 96h ; Control register 2 (RW)
312 0000 ASC21CR3: equ 97h ; Control register 3 (RW)
313
314 ;------------------------------------------------
315 ; Row Digital Interconnects
316 ;
317 ; Note: the following registers are mapped into
318 ; both register bank 0 AND register bank 1.
319 ;------------------------------------------------
320
321 0000 RDI0RI: equ 0B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
322 0000 RDI0SYN: equ 0B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
323 0000 RDI0IS: equ 0B2h ; Row 0 Input Select Register (RW)
324 0000 RDI0LT0: equ 0B3h ; Row 0 Look Up Table Register 0 (RW)
325 0000 RDI0LT1: equ 0B4h ; Row 0 Look Up Table Register 1 (RW)
326 0000 RDI0RO0: equ 0B5h ; Row 0 Output Register 0 (RW)
327 0000 RDI0RO1: equ 0B6h ; Row 0 Output Register 1 (RW)
328
329 ;-----------------------------------------------
330 ; Ram Page Pointers
331 ;-----------------------------------------------
332 0000 CUR_PP: equ 0D0h ; Current Page Pointer
333 0000 STK_PP: equ 0D1h ; Stack Page Pointer
334 0000 IDX_PP: equ 0D3h ; Index Page Pointer
335 0000 MVR_PP: equ 0D4h ; MVI Read Page Pointer
336 0000 MVW_PP: equ 0D5h ; MVI Write Page Pointer
337
338 ;------------------------------------------------
339 ; I2C Configuration Registers
340 ;------------------------------------------------
341 0000 I2C_CFG: equ 0D6h ; I2C Configuration Register (RW)
342 0000 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
343 0000 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
344 0000 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
345 0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
346 0000 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
347 0000 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
348 0000 I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
349 0000 I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
350 0000 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
351 0000 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
352
353 0000 I2C_SCR: equ 0D7h ; I2C Status and Control Register (#)
354 0000 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
355 0000 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
356 0000 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
357 0000 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
358 0000 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
359 0000 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
360 0000 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
361 0000 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
362
363 0000 I2C_DR: equ 0D8h ; I2C Data Register (RW)
364
365 0000 I2C_MSCR: equ 0D9h ; I2C Master Status and Control Register (#)
366 0000 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
367 0000 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
368 0000 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
369 0000 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
370
371 ;------------------------------------------------
372 ; System and Global Resource Registers
373 ;------------------------------------------------
374 0000 INT_CLR0: equ 0DAh ; Interrupt Clear Register 0 (RW)
375 ; Use INT_MSK0 bit field masks
376 0000 INT_CLR1: equ 0DBh ; Interrupt Clear Register 1 (RW)
377 ; Use INT_MSK1 bit field masks
378 0000 INT_CLR2: equ 0DCh ; Interrupt Clear Register 2 (RW)
379 ; Use INT_MSK2 bit field masks
380 0000 INT_CLR3: equ 0DDh ; Interrupt Clear Register 3 (RW)
381 ; Use INT_MSK3 bit field masks
382
383 0000 INT_MSK3: equ 0DEh ; I2C and Software Mask Register (RW)
384 0000 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
385 0000 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
386
387 0000 INT_MSK2: equ 0DFh ; USB Mask Register (RW)
388 0000 INT_MSK2_WAKEUP: equ 80h ; MASK: enable/disable I2C interrupt
389 0000 INT_MSK2_EP4: equ 40h ; MASK: enable/disable SW interrupt
390 0000 INT_MSK2_EP3: equ 20h ; MASK: enable/disable I2C interrupt
391 0000 INT_MSK2_EP2: equ 10h ; MASK: enable/disable SW interrupt
392 0000 INT_MSK2_EP1: equ 08h ; MASK: enable/disable I2C interrupt
393 0000 INT_MSK2_EP0: equ 04h ; MASK: enable/disable SW interrupt
394 0000 INT_MSK2_SOF: equ 02h ; MASK: enable/disable I2C interrupt
395 0000 INT_MSK2_BUS_RESET: equ 01h ; MASK: enable/disable SW interrupt
396
397 0000 INT_MSK0: equ 0E0h ; General Interrupt Mask Register (RW)
398 0000 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
399 0000 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
400 0000 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
401 0000 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
402 0000 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
403 0000 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
404
405 0000 INT_MSK1: equ 0E1h ; Digital PSoC block Mask Register (RW)
406 0000 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
407 0000 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
408 0000 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
409 0000 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
410
411 0000 INT_VC: equ 0E2h ; Interrupt vector register (RC)
412 0000 RES_WDT: equ 0E3h ; Watch Dog Timer Register (W)
413
414 ; DECIMATOR Control Registers
415 0000 DEC_DH: equ 0E4h ; Data High Register (RW)
416 0000 DEC_DL: equ 0E5h ; Data Low Register (RW)
417 0000 DEC_CR0: equ 0E6h ; Data Control Register 0 (RW)
418 0000 DEC_CR1: equ 0E7h ; Data Control Register 1 (RW)
419
420 ;------------------------------------------------------
421 ; MAC Registers
422 ;------------------------------------------------------
423
424 0000 MUL0_X: equ 0E8h ; Multiply Input X Register (W)
425 0000 MUL0_Y: equ 0E9h ; Multiply Input Y Register (W)
426 0000 MUL0_DH: equ 0EAh ; Multiply Result High Byte Register (R)
427 0000 MUL0_DL: equ 0EBh ; Multiply Result Low Byte Register (R)
428
429 0000 ACC0_DR1: equ 0ECh ; Accumulator Data Register 1 (RW)
430 0000 ACC0_DR0: equ 0EDh ; Accumulator Data Register 0 (RW)
431 0000 ACC0_DR3: equ 0EEh ; Accumulator Data Register 3 (RW)
432 0000 ACC0_DR2: equ 0EFh ; Accumulator Data Register 2 (RW)
433
434 ;------------------------------------------------------
435 ; System Status and Control Registers
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