psocconfigtbl.lst

Cypress公司开发的2.4G无线键盘鼠标及其Bridge源代码

   583  0000                    CMP_GO_EN:    equ 64h          ; Comparator Bus 0/1 To Global Out Enable  (RW)
   584  0000                    CMP_GO_EN_GOO5:       equ 80h    ; MASK: Selected Col 1 signal to GOO5
   585  0000                    CMP_GO_EN_GOO1:       equ 40h    ; MASK: Selected Col 1 signal to GOO1
   586  0000                    CMP_GO_EN_SEL1:       equ 30h    ; MASK: Column 1 Signal Select
   587  0000                    CMP_GO_EN_GOO4:       equ 08h    ; MASK: Selected Col 0 signal to GOO4
   588  0000                    CMP_GO_EN_GOO0:       equ 04h    ; MASK: Selected Col 0 signal to GOO0
   589  0000                    CMP_GO_EN_SEL0:       equ 03h    ; MASK: Column 0 Signal Select
   590                          
   591  0000                    CMP_GO_EN1:   equ 65h          ; Comparator Bus 2/3 To Global Out Enable  (RW)
   592  0000                    CMP_GO_EN1_GOO7:      equ 80h    ; MASK: Selected Col 3 signal to GOO5
   593  0000                    CMP_GO_EN1_GOO3:      equ 40h    ; MASK: Selected Col 3 signal to GOO1
   594  0000                    CMP_GO_EN1_SEL3:      equ 30h    ; MASK: Column 3 Signal Select
   595  0000                    CMP_GO_EN1_GOO6:      equ 08h    ; MASK: Selected Col 2 signal to GOO4
   596  0000                    CMP_GO_EN1_GOO2:      equ 04h    ; MASK: Selected Col 2 signal to GOO0
   597  0000                    CMP_GO_EN1_SEL2:      equ 03h    ; MASK: Column 2 Signal Select
   598                          
   599  0000                    AMD_CR1:      equ 66h          ; Analog Modulator Control Register 1      (RW)
   600  0000                    AMD_CR1_AMOD1:        equ 07h    ; MASK: Modulation ctrl for analog column 1
   601                          
   602  0000                    ALT_CR0:      equ 67h          ; Analog Look Up Table (LUT) Register 0    (RW)
   603  0000                    ALT_CR0_LUT1:         equ 0F0h    ; MASK: Look up table 1 selection
   604  0000                    ALT_CR0_LUT0:         equ 0Fh    ; MASK: Look up table 0 selection
   605                          
   606  0000                    ALT_CR1:      equ 68h          ; Analog Look Up Table (LUT) Register 0    (RW)
   607  0000                    ALT_CR0_LUT3:         equ 0F0h    ; MASK: Look up table 3 selection
   608  0000                    ALT_CR0_LUT2:         equ 0Fh    ; MASK: Look up table 2 selection
   609                          
   610  0000                    CLK_CR2:      equ 69h          ; Analog Clock Source Control Register 3   (RW)
   611  0000                    CLK_CR2_ACLK1R:       equ 08h    ; MASK: Analog Column 1 Range 
   612  0000                    CLK_CR2_ACLK0R:       equ 01h    ; MASK: Analog Column 0 Range
   613                          
   614                          ;------------------------------------------------
   615                          ;  USB Registers
   616                          ;------------------------------------------------
   617                          
   618  0000                    USB_CR1:      equ 0C1h          ; USB Control Register 1                   (#)
   619  0000                    USB_CR1_BUS_ACTIVITY: equ 04h    ; MASK: monitors activity on USB bus     (RC)
   620  0000                    USB_CR1_ENABLE_LOCK:  equ 02h    ; MASK: enable/disable auto lock of osc  (RW)
   621  0000                    USB_CR1_REG_ENABLE:   equ 01h    ; MASK: set mode to reg. on/pass thru    (RW)
   622                          
   623  0000                    EP1_CR0:      equ 0C4h          ; EP1 Control Register 0                   (#)
   624  0000                    EP1_CR0_STALL:        equ 80h    ; MASK: enable/disable stall             (RW)
   625  0000                    EP1_CR0_NAK_INT_EN:   equ 20h    ; MASK: enable/disable NAK interrupts    (RW)
   626  0000                    EP1_CR0_ACKD:         equ 10h    ; MASK: set when acked transaction occurs(RC)
   627  0000                    EP1_CR0_MODE:         equ 0Fh    ; MASK: mode control for endpoint        (RW)
   628                          
   629  0000                    EP2_CR0:      equ 0C5h          ; EP2 Control Register 0                   (#)
   630  0000                    EP2_CR0_STALL:        equ 80h    ; MASK: enable/disable stall             (RW)
   631  0000                    EP2_CR0_NAK_INT_EN:   equ 20h    ; MASK: enable/disable NAK interrupts    (RW)
   632  0000                    EP2_CR0_ACKD:         equ 10h    ; MASK: set when acked transaction occurs(RC)
   633  0000                    EP2_CR0_MODE:         equ 0Fh    ; MASK: mode control for endpoint        (RW)
   634                          
   635  0000                    EP3_CR0:      equ 0C6h          ; EP3 Control Register 0                   (#)
   636  0000                    EP3_CR0_STALL:        equ 80h    ; MASK: enable/disable stall             (RW)
   637  0000                    EP3_CR0_NAK_INT_EN:   equ 20h    ; MASK: enable/disable NAK interrupts    (RW)
   638  0000                    EP3_CR0_ACKD:         equ 10h    ; MASK: set when acked transaction occurs(RC)
   639  0000                    EP3_CR0_MODE:         equ 0Fh    ; MASK: mode control for endpoint        (RW)
   640                          
   641  0000                    EP4_CR0:      equ 0C7h          ; EP4 Control Register 0                   (#)
   642  0000                    EP4_CR0_STALL:        equ 80h    ; MASK: enable/disable stall             (RW)
   643  0000                    EP4_CR0_NAK_INT_EN:   equ 20h    ; MASK: enable/disable NAK interrupts    (RW)
   644  0000                    EP4_CR0_ACKD:         equ 10h    ; MASK: set when acked transaction occurs(RC)
   645  0000                    EP4_CR0_MODE:         equ 0Fh    ; MASK: mode control for endpoint        (RW)
   646                          
   647                          ;------------------------------------------------
   648                          ;  Global Digital Interconnects
   649                          ;------------------------------------------------
   650                          
   651  0000                    GDI_O_IN:     equ 0D0h          ; Global Dig Interconnect Odd Inputs Reg   (RW)
   652  0000                    GDI_E_IN:     equ 0D1h          ; Global Dig Interconnect Even Inputs Reg  (RW)
   653  0000                    GDI_O_OU:     equ 0D2h          ; Global Dig Interconnect Odd Outputs Reg  (RW)
   654  0000                    GDI_E_OU:     equ 0D3h          ; Global Dig Interconnect Even Outputs Reg (RW)
   655                          
   656                          ;------------------------------------------------
   657                          ;  AMuxBus Mux Control Registers
   658                          ;------------------------------------------------
   659                          
   660  0000                    MUX_CR0:      equ 0D8h          ; Analog Mux Bus Port 0 Bit Enables Reg    (RW)
   661  0000                    MUX_CR1:      equ 0D9h          ; Analog Mux Bus Port 1 Bit Enables Reg    (RW)
   662  0000                    MUX_CR2:      equ 0DAh          ; Analog Mux Bus Port 2 Bit Enables Reg    (RW)
   663  0000                    MUX_CR3:      equ 0DBh          ; Analog Mux Bus Port 3 Bit Enables Reg    (RW)
   664  0000                    MUX_CR4:      equ 0ECh          ; Analog Mux Bus Port 4 Bit Enables Reg    (RW)
   665  0000                    MUX_CR5:      equ 0EDh          ; Analog Mux Bus Port 5 Bit Enables Reg    (RW)
   666                          
   667                          ;------------------------------------------------
   668                          ;  Clock and System Control Registers
   669                          ;------------------------------------------------
   670                          
   671  0000                    OSC_GO_EN:    equ 0DDh          ; Oscillator to Global Outputs Enable Register (RW)
   672  0000                    OSC_GOEN_SLPINT:      equ 80h	 ; Enable Sleep Timer onto GOE[7]
   673  0000                    OSC_GOEN_VC3:         equ 40h    ; Enable VC3 onto GOE[6]
   674  0000                    OSC_GOEN_VC2:         equ 20h    ; Enable VC2 onto GOE[5]
   675  0000                    OSC_GOEN_VC1:         equ 10h    ; Enable VC1 onto GOE[4]
   676  0000                    OSC_GOEN_SYSCLKX2:    equ 08h    ; Enable 2X SysClk onto GOE[3]
   677  0000                    OSC_GOEN_SYSCLK:      equ 04h    ; Enable 1X SysClk onto GOE[2]
   678  0000                    OSC_GOEN_CLK24M:      equ 02h    ; Enable 24 MHz clock onto GOE[1]
   679  0000                    OSC_GOEN_CLK32K:      equ 01h    ; Enable 32 kHz clock onto GOE[0]
   680                          
   681  0000                    OSC_CR4:      equ 0DEh          ; Oscillator Control Register 4            (RW)
   682  0000                    OSC_CR4_VC3SEL:       equ 03h    ; MASK: System VC3 Clock source
   683                          
   684  0000                    OSC_CR3:      equ 0DFh          ; Oscillator Control Register 3            (RW)
   685                          
   686  0000                    OSC_CR0:      equ 0E0h          ; System Oscillator Control Register 0     (RW)
   687  0000                    OSC_CR0_32K_SELECT:   equ 80h    ; MASK: Enable/Disable External XTAL Osc
   688  0000                    OSC_CR0_PLL_MODE:     equ 40h    ; MASK: Enable/Disable PLL
   689  0000                    OSC_CR0_NO_BUZZ:      equ 20h    ; MASK: Bandgap always powered/BUZZ bandgap
   690  0000                    OSC_CR0_SLEEP:        equ 18h    ; MASK: Set Sleep timer freq/period
   691  0000                    OSC_CR0_SLEEP_512Hz:  equ 00h    ;     Set sleep bits for 1.95ms period
   692  0000                    OSC_CR0_SLEEP_64Hz:   equ 08h    ;     Set sleep bits for 15.6ms period
   693  0000                    OSC_CR0_SLEEP_8Hz:    equ 10h    ;     Set sleep bits for 125ms period
   694  0000                    OSC_CR0_SLEEP_1Hz:    equ 18h    ;     Set sleep bits for 1 sec period
   695  0000                    OSC_CR0_CPU:          equ 07h    ; MASK: Set CPU Frequency
   696  0000                    OSC_CR0_CPU_3MHz:     equ 00h    ;     set CPU Freq bits for 3MHz Operation
   697  0000                    OSC_CR0_CPU_6MHz:     equ 01h    ;     set CPU Freq bits for 6MHz Operation
   698  0000                    OSC_CR0_CPU_12MHz:    equ 02h    ;     set CPU Freq bits for 12MHz Operation
   699  0000                    OSC_CR0_CPU_24MHz:    equ 03h    ;     set CPU Freq bits for 24MHz Operation
   700  0000                    OSC_CR0_CPU_1d5MHz:   equ 04h    ;     set CPU Freq bits for 1.5MHz Operation
   701  0000                    OSC_CR0_CPU_750kHz:   equ 05h    ;     set CPU Freq bits for 750kHz Operation
   702  0000                    OSC_CR0_CPU_187d5kHz: equ 06h    ;     set CPU Freq bits for 187.5kHz Operation
   703  0000                    OSC_CR0_CPU_93d7kHz:  equ 07h    ;     set CPU Freq bits for 93.7kHz Operation
   704                          
   705  0000                    OSC_CR1:      equ 0E1h          ; System VC1/VC2 Divider Control Register  (RW)
   706  0000                    OSC_CR1_VC1:          equ 0F0h    ; MASK: System VC1 24MHz/External Clk divider
   707  0000                    OSC_CR1_VC2:          equ 0Fh    ; MASK: System VC2 24MHz/External Clk divider
   708                          
   709  0000                    OSC_CR2:      equ 0E2h          ; Oscillator Control Register 2            (RW)
   710  0000                    OSC_CR2_PLLGAIN:      equ 80h    ; MASK: High/Low gain
   711  0000                    OSC_CR2_EXTCLKEN:     equ 04h    ; MASK: Enable/Disable External Clock
   712  0000                    OSC_CR2_IMODIS:       equ 02h    ; MASK: Enable/Disable System (IMO) Clock Net
   713  0000                    OSC_CR2_SYSCLKX2DIS:  equ 01h    ; MASK: Enable/Disable 48MHz clock source
   714                          
   715  0000                    VLT_CR:       equ 0E3h          ; Voltage Monitor Control Register         (RW)
   716  0000                    VLT_CR_SMP:           equ 80h    ; MASK: Enable Switch Mode Pump
   717  0000                    VLT_CR_PORLEV:        equ 30h    ; MASK: Mask for Power on Reset level control
   718  0000                    VLT_CR_POR_LOW:       equ 00h    ;   Lowest  Precision Power-on Reset trip point
   719  0000                    VLT_CR_POR_MID:       equ 10h    ;   Middle  Precision Power-on Reset trip point
   720  0000                    VLT_CR_POR_HIGH:      equ 20h    ;   Highest Precision Power-on Reset trip point
   721  0000                    VLT_CR_LVDTBEN:       equ 08h    ; MASK: Enable the CPU Throttle Back on LVD
   722  0000                    VLT_CR_VM:            equ 07h    ; MASK: Mask for Voltage Monitor level setting
   723                          
   724  0000                    VLT_CMP:      equ 0E4h          ; Voltage Monitor Comparators Register     (R)
   725  0000                    VLT_CMP_PUMP:         equ 04h    ; MASK: Vcc below SMP trip level
   726  0000                    VLT_CMP_LVD:          equ 02h    ; MASK: Vcc below LVD trip level
   727  0000                    VLT_CMP_PPOR:         equ 01h    ; MASK: Vcc below PPOR trip level
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