📄 psocconfigtbl.lst
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436 ;
437 ; Note: The following registers are mapped into both
438 ; register bank 0 AND register bank 1.
439 ;------------------------------------------------------
440 0000 CPU_F: equ 0F7h ; CPU Flag Register Access (RO)
441 ; Use FLAG_ masks defined at top of file
442
443 0000 DAC_D: equ 0FDh ; DAC Data Register (RW)
444
445 0000 CPU_SCR1: equ 0FEh ; CPU Status and Control Register #1 (#)
446 0000 CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
447 0000 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
448 0000 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
449 0000 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
450 0000 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
451
452 0000 CPU_SCR0: equ 0FFh ; CPU Status and Control Register #2 (#)
453 0000 CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
454 0000 CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
455 0000 CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
456 0000 CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
457 0000 CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
458
459
460 ;;=============================================================================
461 ;; Register Space, Bank 1
462 ;;=============================================================================
463
464 ;------------------------------------------------
465 ; Port Registers
466 ; Note: Also see this address range in Bank 0.
467 ;------------------------------------------------
468 ; Port 0
469 0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
470 0000 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
471 0000 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
472 0000 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
473
474 ; Port 1
475 0000 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
476 0000 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
477 0000 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
478 0000 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
479
480 ; Port 2
481 0000 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
482 0000 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
483 0000 PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
484 0000 PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
485
486 ; Port 3
487 0000 PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (RW)
488 0000 PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (RW)
489 0000 PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (RW)
490 0000 PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (RW)
491
492 ; Port 4
493 0000 PRT4DM0: equ 10h ; Port 4 Drive Mode 0 (RW)
494 0000 PRT4DM1: equ 11h ; Port 4 Drive Mode 1 (RW)
495 0000 PRT4IC0: equ 12h ; Port 4 Interrupt Control 0 (RW)
496 0000 PRT4IC1: equ 13h ; Port 4 Interrupt Control 1 (RW)
497
498 ; Port 5
499 0000 PRT5DM0: equ 14h ; Port 5 Drive Mode 0 (RW)
500 0000 PRT5DM1: equ 15h ; Port 5 Drive Mode 1 (RW)
501 0000 PRT5IC0: equ 16h ; Port 5 Interrupt Control 0 (RW)
502 0000 PRT5IC1: equ 17h ; Port 5 Interrupt Control 1 (RW)
503
504 ; Port 7
505 0000 PRT7DM0: equ 1Ch ; Port 7 Drive Mode 0 (RW)
506 0000 PRT7DM1: equ 1Dh ; Port 7 Drive Mode 1 (RW)
507 0000 PRT7IC0: equ 1Eh ; Port 7 Interrupt Control 0 (RW)
508 0000 PRT7IC1: equ 1Fh ; Port 7 Interrupt Control 1 (RW)
509
510 ;------------------------------------------------
511 ; Digital PSoC(tm) block Registers
512 ; Note: Also see this address range in Bank 0.
513 ;------------------------------------------------
514
515 ; Digital PSoC block 00, Basic Type B
516 0000 DBB00FN: equ 20h ; Function Register (RW)
517 0000 DBB00IN: equ 21h ; Input Register (RW)
518 0000 DBB00OU: equ 22h ; Output Register (RW)
519
520 ; Digital PSoC block 01, Basic Type B
521 0000 DBB01FN: equ 24h ; Function Register (RW)
522 0000 DBB01IN: equ 25h ; Input Register (RW)
523 0000 DBB01OU: equ 26h ; Output Register (RW)
524
525 ; Digital PSoC block 02, Communications Type B
526 0000 DCB02FN: equ 28h ; Function Register (RW)
527 0000 DCB02IN: equ 29h ; Input Register (RW)
528 0000 DCB02OU: equ 2Ah ; Output Register (RW)
529
530 ; Digital PSoC block 03, Communications Type B
531 0000 DCB03FN: equ 2Ch ; Function Register (RW)
532 0000 DCB03IN: equ 2Dh ; Input Register (RW)
533 0000 DCB03OU: equ 2Eh ; Output Register (RW)
534
535 ;------------------------------------------------
536 ; PMA Write and Read Registers
537 ;------------------------------------------------
538
539 0000 PMA0_WA: equ 40h ; PMA Write Pointer Register (RW)
540 0000 PMA1_WA: equ 41h ; PMA Write Pointer Register (RW)
541 0000 PMA2_WA: equ 42h ; PMA Write Pointer Register (RW)
542 0000 PMA3_WA: equ 43h ; PMA Write Pointer Register (RW)
543 0000 PMA4_WA: equ 44h ; PMA Write Pointer Register (RW)
544 0000 PMA5_WA: equ 45h ; PMA Write Pointer Register (RW)
545 0000 PMA6_WA: equ 46h ; PMA Write Pointer Register (RW)
546 0000 PMA7_WA: equ 47h ; PMA Write Pointer Register (RW)
547
548 0000 PMA0_RA: equ 50h ; PMA Read Pointer Register (RW)
549 0000 PMA1_RA: equ 51h ; PMA Read Pointer Register (RW)
550 0000 PMA2_RA: equ 52h ; PMA Read Pointer Register (RW)
551 0000 PMA3_RA: equ 53h ; PMA Read Pointer Register (RW)
552 0000 PMA4_RA: equ 54h ; PMA Read Pointer Register (RW)
553 0000 PMA5_RA: equ 55h ; PMA Read Pointer Register (RW)
554 0000 PMA6_RA: equ 56h ; PMA Read Pointer Register (RW)
555 0000 PMA7_RA: equ 57h ; PMA Read Pointer Register (RW)
556
557
558
559 ;------------------------------------------------
560 ; System and Global Resource Registers
561 ; Note: Also see this address range in Bank 0.
562 ;------------------------------------------------
563
564 0000 CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
565 0000 CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
566 0000 CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
567
568 0000 CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
569 0000 CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
570 0000 CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
571 0000 CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
572
573 0000 ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
574 0000 ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
575 0000 ABF_CR0_ABUF1EN: equ 20h ; MASK: Enable ACol 1 analog buffer (P0[5])
576 0000 ABF_CR0_ABUF0EN: equ 08h ; MASK: Enable ACol 0 analog buffer (P0[3])
577 0000 ABF_CR0_BYPASS: equ 02h ; MASK: Bypass the analog buffers
578 0000 ABF_CR0_PWR: equ 01h ; MASK: High power mode on all analog buffers
579
580 0000 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
581 0000 AMD_CR0_AMOD0: equ 07h ; MASK: Modulation source for analog column 1
582
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