📄 psocconfigtbl.lst
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142 0000 USB_CR0_ENABLE: equ 80h ; MASK: enable/disable USB SIE (RW)
143 0000 USB_CR0_DEVICE_ADDR: equ 7Fh ; MASK: USB Device Address (RW)
144
145 0000 USBIO_CR0: equ 4Bh ; USB IO Control Register 0 (#)
146 0000 USBIO_CR0_TEN: equ 80h ; MASK: enable/disable manual tx on D+ D-(RW)
147 0000 USBIO_CR0_TSE0: equ 40h ; MASK: transmit a single ended 0 (RW)
148 0000 USBIO_CR0_TD: equ 20h ; MASK: transmit J or K state on Bus (RW)
149 0000 USBIO_CR0_RD: equ 01h ; MASK: read state of differential rx (R)
150
151 0000 USBIO_CR1: equ 4Ch ; USB IO Control Register 0 (#)
152 0000 USBIO_CR1_IOMODE: equ 80h ; MASK: select Bit Bang Mode/USB Mode (RW)
153 0000 USBIO_CR1_DRIVE_MODE: equ 40h ; MASK: select CMOS mode/Open Drain mode (RW)
154 0000 USBIO_CR1_DPI: equ 20h ; MASK: drive D+ high/low (RW)
155 0000 USBIO_CR1_DMI: equ 10h ; MASK: drive D- high/low (RW)
156 0000 USBIO_CR1_PS2PUEN: equ 08h ; MASK: enable/disable 5K Pullup on D+/D-(RW)
157 0000 USBIO_CR1_USBPUEN: equ 04h ; MASK: enable/disable USB Pullup on D+ (RW)
158 0000 USBIO_CR1_DPO: equ 02h ; MASK: read D+ pin (R)
159 0000 USBIO_CR1_DMO: equ 01h ; MASK: read D- pin (R)
160
161
162 ;------------------------------------------------
163 ; USB Endpoint Registers
164 ;------------------------------------------------
165
166 0000 EP1_CNT1: equ 4Eh ; Endpoint 1 Count Register 1 (#)
167 0000 EP1_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
168 0000 EP1_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
169 0000 EP1_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
170
171 0000 EP1_CNT: equ 4Fh ; Endpoint 1 Count Register 0 (RW)
172
173 0000 EP2_CNT1: equ 50h ; Endpoint 2 Count Register 1 (#)
174 0000 EP2_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
175 0000 EP2_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
176 0000 EP2_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
177
178 0000 EP2_CNT: equ 51h ; Endpoint 2 Count Register 0 (RW)
179
180 0000 EP3_CNT1: equ 52h ; Endpoint 3 Count Register 1 (#)
181 0000 EP3_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
182 0000 EP3_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
183 0000 EP3_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
184
185 0000 EP3_CNT: equ 53h ; Endpoint 3 Count Register 0 (RW)
186
187 0000 EP4_CNT1: equ 54h ; Endpoint 4 Count Register 1 (#)
188 0000 EP4_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
189 0000 EP4_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
190 0000 EP4_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
191
192 0000 EP4_CNT: equ 55h ; Endpoint 4 Count Register 0 (RW)
193
194 0000 EP0_CR: equ 56h ; Endpoint 0 Control Register 0 (#)
195 0000 EP0_CR_SETUP_RCVD: equ 80h ; MASK: Setup received (RC)
196 0000 EP0_CR_IN_RCVD: equ 40h ; MASK: IN received (RC)
197 0000 EP0_CR_OUT_RCVD: equ 20h ; MASK: OUT received (RC)
198 0000 EP0_CR_ACKD: equ 10h ; MASK: Acked transaction (RC)
199 0000 EP0_CR_MODE: equ 0Fh ; MASK: Mode response for endpoint (RW)
200
201 ; ------------------------------------------------------------------------------
202 ; The following defines are depricated. Left here for compatibility.
203 0000 EP0_CR0: equ 56h ; Endpoint 0 Control Register 0 (#)
204 0000 EP0_CR0_SETUP_RCVD: equ 80h ; MASK: Setup received (RC)
205 0000 EP0_CR0_IN_RCVD: equ 40h ; MASK: IN received (RC)
206 0000 EP0_CR0_OUT_RCVD: equ 20h ; MASK: OUT received (RC)
207 0000 EP0_CR0_ACKD: equ 10h ; MASK: Acked transaction (RC)
208 0000 EP0_CR0_MODE: equ 0Fh ; MASK: Mode response for endpoint (RW)
209 ; ------------------------------------------------------------------------------
210
211 0000 EP0_CNT: equ 57h ; Endpoint 0 Count Register (#)
212 0000 EP0_CNT_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
213 0000 EP0_CNT_DATA_VALID: equ 40h ; MASK: read error status on rx data (RC)
214 0000 EP0_CNT_BYTE_CNT: equ 0Fh ; MASK: MSB of 9-bit count value (RW)
215
216 0000 EP0_DR0: equ 58h ; Endpoint 0 Data Register 0 (RW)
217 0000 EP0_DR1: equ 59h ; Endpoint 0 Data Register 1 (RW)
218 0000 EP0_DR2: equ 5Ah ; Endpoint 0 Data Register 2 (RW)
219 0000 EP0_DR3: equ 5Bh ; Endpoint 0 Data Register 3 (RW)
220 0000 EP0_DR4: equ 5Ch ; Endpoint 0 Data Register 4 (RW)
221 0000 EP0_DR5: equ 5Dh ; Endpoint 0 Data Register 5 (RW)
222 0000 EP0_DR6: equ 5Eh ; Endpoint 0 Data Register 6 (RW)
223 0000 EP0_DR7: equ 5Fh ; Endpoint 0 Data Register 7 (RW)
224
225 ;-------------------------------------
226 ; Analog Control Registers
227 ;-------------------------------------
228 0000 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
229 0000 AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
230 0000 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
231
232 0000 AMUXCFG: equ 61h ; Analog Mux Bus Configuration Register (RW)
233 0000 AMUXCFG_BCOL0_MUX: equ 80h ; MASK: select AMuxBusB for Col1 input (RW)
234 0000 AMUXCFG_ACOL0_MUX: equ 40h ; MASK: select AMuxBusA for Col0 input (RW)
235 0000 AMUXCFG_INTCAP: equ 30h ; MASK: select pins for static operation (RW)
236 0000 AMUXCFG_MUXCLK: equ 0Eh ; MASK: select precharge clock source (RW)
237 0000 AMUXCFG_EN: equ 01h ; MASK: enable/disable MUXCLK (RW)
238
239 0000 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
240 0000 ARF_CR_HBE: equ 40h ; MASK: Bias level control
241 0000 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
242 0000 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
243 0000 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
244
245 0000 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
246 0000 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
247 0000 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
248 0000 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
249 0000 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
250
251 0000 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
252 0000 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
253 0000 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
254 0000 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
255 0000 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
256
257 0000 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
258 0000 CMP_CR1_CLDIS1: equ 20h ; MASK: Column 1 comparator bus synch
259 0000 CMP_CR1_CLDIS0: equ 10h ; MASK: Column 0 comparator bus synch
260 0000 CMP_CR1_CLDIX1: equ 02h ; MASK: Column 1 comparator bus synch
261 0000 CMP_CR1_CLDIX0: equ 01h ; MASK: Column 0 comparator bus synch
262
263 ;-----------------------------------------------
264 ; Global General Purpose Data Registers
265 ;-----------------------------------------------
266 0000 TMP_DR0: equ 6Ch ; Temporary Data Register 0 (RW)
267 0000 TMP_DR1: equ 6Dh ; Temporary Data Register 1 (RW)
268 0000 TMP_DR2: equ 6Eh ; Temporary Data Register 2 (RW)
269 0000 TMP_DR3: equ 6Fh ; Temporary Data Register 3 (RW)
270
271 ;---------------------------------------------------
272 ; Analog PSoC block Registers
273 ;
274 ; Note: the following registers are mapped into
275 ; both register bank 0 AND register bank 1.
276 ;---------------------------------------------------
277
278 ; Continuous Time PSoC block Type B Row 0 Col 0
279 0000 ACB00CR3: equ 70h ; Control register 3 (RW)
280 0000 ACB00CR0: equ 71h ; Control register 0 (RW)
281 0000 ACB00CR1: equ 72h ; Control register 1 (RW)
282 0000 ACB00CR2: equ 73h ; Control register 2 (RW)
283
284 ; Continuous Time PSoC block Type B Row 0 Col 1
285 0000 ACB01CR3: equ 74h ; Control register 3 (RW)
286 0000 ACB01CR0: equ 75h ; Control register 0 (RW)
287 0000 ACB01CR1: equ 76h ; Control register 1 (RW)
288 0000 ACB01CR2: equ 77h ; Control register 2 (RW)
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