📄 mcp2510.h
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#ifndef _MCP2510_H_
#define _MCP2510_H_
//********************** MCP2510 Regrister *********************************
// Register offsets into the transmit buffers.
/*#define MCP2510REG_TXBnCTRL 0
#define MCP2510REG_TXBnSIDH 1
#define MCP2510REG_TXBnSIDL 2
#define MCP2510REG_TXBnEID8 3
#define MCP2510REG_TXBnEID0 4
#define MCP2510REG_TXBnDLC 5
#define MCP2510REG_TXBnD0 6
#define MCP2510REG_TXBnD1 7
#define MCP2510REG_TXBnD2 8
#define MCP2510REG_TXBnD3 9
#define MCP2510REG_TXBnD4 10
#define MCP2510REG_TXBnD5 11
#define MCP2510REG_TXBnD6 12
#define MCP2510REG_TXBnD7 13
#define MCP2510REG_CANSTAT 14
#define MCP2510REG_CANCTRL 15
//
#define MCP2510LREG_SIDH 0
#define MCP2510LREG_SIDL 1
#define MCP2510LREG_EID8 2
#define MCP2510LREG_EID0 3
*/
//#define TXB0CTRL 0
//#define TXB0SIDH 1
//#define TXB0SIDL 2
//#define TXBnEID8 3
//#define TXBnEID0 4
//#define TXBnDLC 5
//#define TXBnD0 6
//#define TXBnD1 7
//#define TXBnD2 8
//#define TXBnD3 9
//#define TXBnD4 10
//#define TXBnD5 11
//#define TXBnD6 12
//#define TXBnD7 13
#define CANSTAT 14
#define CANCTRL 15
//
#define SIDH 0
#define SIDL 1
#define EID8 2
#define EID0 3
//******************* Bits in the TXBnCTRL registers.***************************
#define TXB_TXBUFE_M 0x80
#define TXB_ABTF_M 0x40
#define TXB_MLOA_M 0x20
#define TXB_TXERR_M 0x10
#define TXB_TXREQ_M 0x08
#define TXB_TXIE_M 0x04
#define TXB_TXP10_M 0x03
#define DLC_MASK 0x0F
#define RTR_MASK 0x40
#define EXIDE 0x08
#define TXB0CTRL 0x30
#define TXB0SIDH 0x31
#define TXB0SIDL 0x32
#define TXB0EID8 0x33
#define TXB0EID0 0x34
#define TXB0DLC 0x35
#define TXB0D0 0x36
#define TXB0D1 0x37
#define TXB0D2 0x38
#define TXB0D3 0x39
#define TXB0D4 0x3a
#define TXB0D5 0x3b
#define TXB0D6 0x3c
#define TXB0D7 0x3d
#define TXB1CTRL 0x40
#define TXB1SIDH 0x41
#define TXB1SIDL 0x42
#define TXB1EID8 0x43
#define TXB1EID0 0x44
#define TXB1DLC 0x45
#define TXB1D0 0x46
#define TXB1D1 0x47
#define TXB1D2 0x48
#define TXB1D3 0x49
#define TXB1D4 0x4a
#define TXB1D5 0x4b
#define TXB1D6 0x4c
#define TXB1D7 0x4d
#define TXB2CTRL 0x50
#define TXB2SIDH 0x51
#define TXB2SIDL 0x52
#define TXB2EID8 0x53
#define TXB2EID0 0x54
#define TXB2DLC 0x55
#define TXB2D0 0x56
#define TXB2D1 0x57
#define TXB2D2 0x58
#define TXB2D3 0x59
#define TXB2D4 0x5a
#define TXB2D5 0x5b
#define TXB2D6 0x5c
#define TXB2D7 0x5d
#define TXB1CTRL 0x40
#define TXB1SIDH 0x41
#define TXB2CTRL 0x50
#define TXB2SIDH 0x51
#define TXPRIOHIGH 0x03
#define TXPRIOHIGHLOW 0x02
#define TXPRIOLOWHIGH 0x01
#define TXPRIOLOW 0x00
#define TXB_EXIDE_M 0x08 // In TXBnSIDL
#define TXB_RTR_M 0x40 // In TXBnDLC
#define RXB_IDE_M 0x08 // In RXBnSIDL
#define RXB_RTR_M 0x40 // In RXBnDLC
#define BFPCTRL 0x0C
#define B2RTS 0x20
#define B1RTS 0x10
#define B0RTS 0x08
#define B2RTSM 0x04
#define B1RTSM 0x02
#define B0RTSM 0x01
#define TEC 0x1C
#define REC 0x1D
#define CLKCTRL CANCTRL
#define RXB0SIDH 0x61
#define RXB1SIDH 0x71
#define RXF0SIDH 0
#define RXF0SIDL 1
#define RXF0EID8 2
#define RXF0EID0 3
#define RXF1SIDH 4
#define RXF1SIDL 5
#define RXF1EID8 6
#define RXF1EID0 7
#define RXF2SIDH 8
#define RXF2SIDL 9
#define RXF2EID8 10
#define RXF2EID0 11
#define RXF3SIDH 16
#define RXF3SIDL 17
#define RXF3EID8 18
#define RXF3EID0 19
#define RXF4SIDH 20
#define RXF4SIDL 21
#define RXF4EID8 22
#define RXF4EID0 23
#define RXF5SIDH 24
#define RXF5SIDL 25
#define RXF5EID8 26
#define RXF5EID0 27
#define RXF_EXIDE_M 0x08
#define RXM0SIDH 0x20
#define RXM0SIDL 0x21
#define RXM0EID8 0x22
#define RXM0EID0 0x23
#define RXM1SIDH 0x24
#define RXM1SIDL 0x25
#define RXM1EID8 0x26
#define RXM1EID0 0x27
#define CNF3 0x28
#define CNF2 0x29
#define CNF1 0x2A
#define CANINTE 0x2B
#define CANINTF 0x2C
#define EFLG 0x2D
#define TXRTSCTRL 0x0D
#define EFLG_RX1OVR 0x80
#define EFLG_RX0OVR 0x40
#define EFLG_TXBO 0x20
#define EFLG_TXEP 0x10
#define EFLG_RXEP 0x08
#define EFLG_TXWAR 0x04
#define EFLG_RXWAR 0x02
#define EFLG_EWARN 0x01
#define SJW1 0x00
#define SJW2 0x40
#define SJW3 0x80
#define SJW4 0xC0
#define BTLMODE_CNF3 0x80
#define SAMP1 0x00
#define SAMP3 0x40
#define SEG1 0x00
#define SEG2 0x01
#define SEG3 0x02
#define SEG4 0x03
#define SEG5 0x04
#define SEG6 0x05
#define SEG7 0x06
#define SEG8 0x07
#define BRP1 0x00
#define BRP2 0x01
#define BRP3 0x02
#define BRP4 0x03
#define BRP5 0x04
#define BRP6 0x05
#define BRP7 0x06
#define BRP8 0x07
#define IVRIE 0x80
#define WAKIE 0x40
#define ERRIE 0x20
#define TX2IE 0x10
#define TX1IE 0x08
#define TX0IE 0x04
#define RX1IE 0x02
#define RX0IE 0x01
#define DIS_INT 0x00
#define IVRINT 0x80
#define WAKINT 0x40
#define ERRINT 0x20
#define TX2INT 0x10
#define TX1INT 0x08
#define TX0INT 0x04
#define RX1INT 0x02
#define RX0INT 0x01
#define NO_INT 0x00
#define RXB0CTRL 0x60
#define RXB1CTRL 0x70
#define RXB_RXRDY 0x80
#define RXB_RXM1 0x40
#define RXB_RXM0 0x20
#define RXB_RX_ANY 0x60
#define RXB_RX_EXT 0x40
#define RXB_RX_STD 0x20
#define RXB_RX_STDEXT 0x00
#define RXB_RXMx_M 0x60
// #define RXB_RXIE_M 0x10
#define RXB_RXRTR 0x08 // In RXBnCTRL
#define RXB_BUKT 0x04
#define RXB_BUKT_RO 0x02
#define RXB_FILHIT 0x01
#define RXB_FILHIT2 0x04
#define RXB_FILHIT1 0x02
#define RXB_FILHIT_M 0x07
#define RXB_RXF5 0x05
#define RXB_RXF4 0x04
#define RXB_RXF3 0x03
#define RXB_RXF2 0x02
#define RXB_RXF1 0x01
#define RXB_RXF0 0x00
#define CLKEN 0x04
#define CLK1 0x00
#define CLK2 0x01
#define CLK4 0x02
#define CLK8 0x03
#define MODE_NORMAL 0x00
#define MODE_SLEEP 0x20
#define MODE_LOOPBACK 0x40
#define MODE_LISTENONLY 0x60
#define MODE_CONFIG 0x80
#define ABORT 0x10
typedef uint8 BOOL;
typedef enum{
BandRate_125kbps,
BandRate_250kbps,
BandRate_500kbps,
BandRate_1Mbps
}CanBandRate;
typedef struct{
uint8 TXBnSIDH;
uint8 TXBnSIDL;
uint8 TXBnEID8;
uint8 TXBnEID0;
uint8 TXBnDLC;
uint8 TXBmDn[8];
}CANTXDATA;
typedef struct{
uint8 RXBnSIDH;
uint8 RXBnSIDL;
uint8 RXBnEID8;
uint8 RXBnEID0;
uint8 RXBnDLC;
uint8 RXBmDn[8];
}CANRXDATAREG;
typedef struct{
BOOL isExt;
BOOL isRTR;
uint32 id;
uint8 rxNum;
uint8 rxData[8];
}CANRXDATA;
void MCPWriteByte(uint8 addr,uint8 data);
uint8 MCPReadByte(uint8 addr);
uint8 MCPReadCANStatus(void);
void CAN_Modefybits( uint8 address, uint8 data, uint8 mask );
void MCP_ReadSeq(uint8 address,uint8 *pdata,uint8 nlength);
void MCP_WriteSeq(uint8 address, uint8* pdata, uint8 nlength);
void CANReset(void);
void CAN_Init(void);
void CAN_Test(void);
CANRXDATA CAN_ReadData(void);
void CAN_WriteData(uint8 ntxbuffer0_2,uint32 id, uint8 *pdata, uint8 dlc, BOOL isExt, BOOL rxRTR);
#endif
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