📄 registers.lst
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ARM COMPILER V2.00d, registers 23/10/05 18:16:19 PAGE 1
ARM COMPILER V2.00d, COMPILATION OF MODULE registers
OBJECT MODULE PLACED IN .\Flash\registers.obj
COMPILER INVOKED BY: C:\KEIL\ARM\BIN\CA.EXE registers.c THUMB OPTIMIZE(7,SPEED) BROWSE DEBUG PRINT(.\FLASH\REGISTERS.LST
-) TABS(4) OBJECT(.\Flash\registers.obj)
stmt level source
1 // Register initialization required to support the MCB2130 board and the wheather station
2 #include <LPC213x.H> // LPC21xx definitions
3
4 // UART 1 Tx and Rx pin assignment, AD1 and DAC assignments
5 void init_registers() {
6 1 // Pin Select register 0
7 1 PINSEL0 = 0x00050020; // Enable RxD1 and TxD1 on pins P0.8 & P0.9
8 1 // Enable Cap 1.0 on pins P0.10 & Cap 1.1 on pin P0.11
9 1 // the 20 is for pin 2 as timer 0 capture 0.0
10 1 // setup IO pin directions for outputs
11 1 IODIR1 = 0x00FF0000; // P1.16..23 defined as Outputs
12 1 // Setup A/D
13 1 // AD0CR = 0x00200402; // Setup A/D: 10-bit AIN0 (ch 0 and 1) @ 3MHz
14 1 PINSEL1 = 0x01400000; // enable DAC was 0x01080000
15 1 // was changed to 0x01000000 to disable DAC
16 1 // chanded to 0x01400000 enable A/D ch 0 & 1
17 1 // enable interrupts // currectly DAC is disabled, hence PINSEL1 = 0x01000000
18 1 // Default for GPIO P0.16..18 are used for position
19 1 VICIntEnable = 0x000020B0; // Enable Timer0 (0x00000010),
20 1 // Timer 1 (0x00000020),
21 1 // UART 1 (0x00000080),
22 1 // and RTC Interrupt (0x00002000)
23 1 }
24 //
25
ARM COMPILER V2.00d, registers 23/10/05 18:16:19 PAGE 2
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** PUBLICS:
PUBLIC init_registers?T
*** CODE SEGMENT '?PR?init_registers?T?registers':
7: PINSEL0 = 0x00050020; // Enable RxD1 and TxD1 on pins P0.8 & P0.9
00000000 4800 LDR R1,=0x50020
00000002 4800 LDR R0,=0xE002C000
00000004 6001 STR R1,[R0,#0x0]
11: IODIR1 = 0x00FF0000; // P1.16..23 defined as Outputs
00000006 4800 LDR R1,=0xFF0000
00000008 4800 LDR R0,=0xE0028018
0000000A 6001 STR R1,[R0,#0x0]
14: PINSEL1 = 0x01400000; // enable DAC was 0x01080000
0000000C 4800 LDR R1,=0x1400000
0000000E 4800 LDR R0,=0xE002C004
00000010 6001 STR R1,[R0,#0x0]
19: VICIntEnable = 0x000020B0; // Enable Timer0 (0x00000010),
00000012 4800 LDR R1,=0x20B0
00000014 4800 LDR R0,=0xFFFFF010
00000016 6001 STR R1,[R0,#0x0]
23: }
00000018 4770 BX R14
0000001A ENDP ; 'init_registers?T'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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