📄 clock.lst
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ARM COMPILER V2.00d, clock 23/10/05 18:16:18 PAGE 1
ARM COMPILER V2.00d, COMPILATION OF MODULE clock
OBJECT MODULE PLACED IN .\Flash\clock.obj
COMPILER INVOKED BY: C:\KEIL\ARM\BIN\CA.EXE clock.c THUMB OPTIMIZE(7,SPEED) BROWSE DEBUG PRINT(.\FLASH\CLOCK.LST) TABS(4
-) OBJECT(.\Flash\clock.obj)
stmt level source
1 /******************************************************************************/
2 /* This file is part of the kp development */
3 /* Copyright kp */
4 /******************************************************************************/
5 /* */
6 /* Clock.C: Low Level clock Routines */
7 /* */
8 /******************************************************************************/
9
10 #include <LPC213x.H> // LPC21xx definitions
11 #include <bsp.h> // include board support package
12
13 extern void set_LED (unsigned char led_no, unsigned char led_cmd);
14
15 // Real-time clock interrupt routine
16 void rtc (void) __irq {
17 1 if ((SEC % 2)==0) set_LED(2,1);
18 1 else set_LED(2,0);
19 1 ILR = 1; // Clear RTC interrupt flag
20 1 VICVectAddr = 0; // Acknowledge Interrupt
21 1 }
22
23 void init_clock (void) { // Initialize clock Interface
24 1 CCR = 0x02; // reset CTC
25 1 CCR = 0x00; // bring CTC out of reset
26 1 CCR = 0x01; // enable CTR counter
27 1 CIIR = AMR = 0x00; // don't select counter or alarm interrupts
28 1 SEC = 13; // init clock value registers
29 1 MIN = 58;
30 1 HOUR = 12;
31 1 // DOM =
32 1 // DOW =
33 1 // DOY =
34 1 MONTH = 8;
35 1 YEAR = 2005;
36 1
37 1 // setup interrupt for every second
38 1 CIIR = 0x01; // gererate and interrupt each second
39 1
40 1 // The 15 Mhz come from a cclk=60 Mhz, w/ VPBDIV=0 (or div 4) (see startup.s)
41 1 PREINT = 456; // int(15mhz/32768)-1 = 456
42 1 PREFRAC = 25024; // 15Mhz - ((PREINT+1)*32678) = 25,024
43 1 VICVectAddr3 = (unsigned long)rtc; // set interrupt vector in 0
44 1 VICVectCntl3 = 0x20 | 13; // use it for real-time clock
45 1 // VICIntEnable = 0x00002030; // Enable Timer0, 1, and RTC Interrupt
46 1 }
47
48 /*
49 #define ILR (*((volatile unsigned char *) 0xE0024000))
50 #define CTC (*((volatile unsigned short*) 0xE0024004))
51 #define CCR (*((volatile unsigned char *) 0xE0024008))
52 #define CIIR (*((volatile unsigned char *) 0xE002400C))
53 #define AMR (*((volatile unsigned char *) 0xE0024010))
54 #define CTIME0 (*((volatile unsigned long *) 0xE0024014))
55 #define CTIME1 (*((volatile unsigned long *) 0xE0024018))
56 #define CTIME2 (*((volatile unsigned long *) 0xE002401C))
57
58 #define SEC (*((volatile unsigned char *) 0xE0024020))
ARM COMPILER V2.00d, clock 23/10/05 18:16:18 PAGE 2
59 #define MIN (*((volatile unsigned char *) 0xE0024024))
60 #define HOUR (*((volatile unsigned char *) 0xE0024028))
61 #define DOM (*((volatile unsigned char *) 0xE002402C))
62 #define DOW (*((volatile unsigned char *) 0xE0024030))
63 #define DOY (*((volatile unsigned short*) 0xE0024034))
64 #define MONTH (*((volatile unsigned char *) 0xE0024038))
65 #define YEAR (*((volatile unsigned short*) 0xE002403C))
66
67 #define ALSEC (*((volatile unsigned char *) 0xE0024060))
68 #define ALMIN (*((volatile unsigned char *) 0xE0024064))
69 #define ALHOUR (*((volatile unsigned char *) 0xE0024068))
70 #define ALDOM (*((volatile unsigned char *) 0xE002406C))
71 #define ALDOW (*((volatile unsigned char *) 0xE0024070))
72 #define ALDOY (*((volatile unsigned short*) 0xE0024074))
73 #define ALMON (*((volatile unsigned char *) 0xE0024078))
74 #define ALYEAR (*((volatile unsigned short*) 0xE002407C))
75
76 #define PREINT (*((volatile unsigned short*) 0xE0024080))
77 #define PREFRAC (*((volatile unsigned short*) 0xE0024084))
78 */
ARM COMPILER V2.00d, clock 23/10/05 18:16:18 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN CODE16 (set_LED?T)
EXTERN CODE32 (set_LED?A)
EXTERN CODE32 (?C?SDIV?A)
*** PUBLICS:
PUBLIC rtc?A
PUBLIC init_clock?T
*** CODE SEGMENT '?PR?rtc?A?clock':
16: void rtc (void) __irq {
00000000 E92D5F0F STMDB R13!,{R0-R3,R8-R12,LR}
17: if ((SEC % 2)==0) set_LED(2,1);
00000004 E5100000 LDR R0,=0xE0024020
00000008 E5D00000 LDRB R0,[R0,#0x0]
0000000C E3A01002 MOV R1,#0x2
00000010 EBFFFFFA BL ?C?SDIV?A ; Targ=0x0 ; ?C?SDIV?A
00000014 E1A01000 MOV R1,R0
00000018 E3510000 CMP R1,#0x0000
0000001C 1A000003 BNE L_1 ; Targ=0x30
00000020 E3A00002 MOV R0,#0x2
00000024 E3A01001 MOV R1,#0x1
00000028 EBFFFFF4 BL set_LED?A ; Targ=0x0
0000002C EA000002 B L_2 ; Targ=0x3C
00000030 L_1:
18: else set_LED(2,0);
00000030 E3A00002 MOV R0,#0x2
00000034 E3A01000 MOV R1,#0x0
00000038 EBFFFFF0 BL set_LED?A ; Targ=0x0
0000003C L_2:
19: ILR = 1; // Clear RTC interrupt flag
0000003C E3A01001 MOV R1,#0x1
00000040 E5100000 LDR R0,=0xE0024000
00000044 E5C01000 STRB R1,[R0,#0x0]
20: VICVectAddr = 0; // Acknowledge Interrupt
00000048 E3A01000 MOV R1,#0x0
0000004C E5100000 LDR R0,=0xFFFFF030
00000050 E5801000 STR R1,[R0,#0x0]
21: }
00000054 E8BD5F0F LDMIA R13!,{R0-R3,R8-R12,LR}
00000058 E25EF004 SUBS R15,R14,#0x0004
0000005C ENDP ; 'rtc?A'
*** CODE SEGMENT '?PR?init_clock?T?clock':
24: CCR = 0x02; // reset CTC
00000000 2102 MOV R1,#0x2
00000002 4800 LDR R0,=0xE0024008
00000004 7001 STRB R1,[R0,#0x0]
25: CCR = 0x00; // bring CTC out of reset
00000006 2100 MOV R1,#0x0
00000008 4800 LDR R0,=0xE0024008
0000000A 7001 STRB R1,[R0,#0x0]
26: CCR = 0x01; // enable CTR counter
0000000C 2101 MOV R1,#0x1
0000000E 4800 LDR R0,=0xE0024008
00000010 7001 STRB R1,[R0,#0x0]
27: CIIR = AMR = 0x00; // don't select counter or alarm interrupts
00000012 2100 MOV R1,#0x0
00000014 4800 LDR R0,=0xE0024010
00000016 7001 STRB R1,[R0,#0x0]
00000018 2100 MOV R1,#0x0
0000001A 4800 LDR R0,=0xE002400C
0000001C 7001 STRB R1,[R0,#0x0]
28: SEC = 13; // init clock value registers
ARM COMPILER V2.00d, clock 23/10/05 18:16:18 PAGE 4
0000001E 210D MOV R1,#0xD
00000020 4800 LDR R0,=0xE0024020
00000022 7001 STRB R1,[R0,#0x0]
29: MIN = 58;
00000024 213A MOV R1,#0x3A
00000026 4800 LDR R0,=0xE0024024
00000028 7001 STRB R1,[R0,#0x0]
30: HOUR = 12;
0000002A 210C MOV R1,#0xC
0000002C 4800 LDR R0,=0xE0024028
0000002E 7001 STRB R1,[R0,#0x0]
34: MONTH = 8;
00000030 2108 MOV R1,#0x8
00000032 4800 LDR R0,=0xE0024038
00000034 7001 STRB R1,[R0,#0x0]
35: YEAR = 2005;
00000036 4800 LDRH R1,=0x7D5
00000038 4800 LDR R0,=0xE002403C
0000003A 8001 STRH R1,[R0,#0x0]
38: CIIR = 0x01; // gererate and interrupt each second
0000003C 2101 MOV R1,#0x1
0000003E 4800 LDR R0,=0xE002400C
00000040 7001 STRB R1,[R0,#0x0]
41: PREINT = 456; // int(15mhz/32768)-1 = 456
00000042 4972 LDRH R1,=0x1C8
00000044 4800 LDR R0,=0xE0024080
00000046 8001 STRH R1,[R0,#0x0]
42: PREFRAC = 25024; // 15Mhz - ((PREINT+1)*32678) = 25,024
00000048 4800 LDRH R1,=0x61C0
0000004A 4800 LDR R0,=0xE0024084
0000004C 8001 STRH R1,[R0,#0x0]
43: VICVectAddr3 = (unsigned long)rtc; // set interrupt vector in 0
0000004E 4900 LDR R1,=rtc?A ; rtc?A
00000050 4800 LDR R0,=0xFFFFF10C
00000052 6001 STR R1,[R0,#0x0]
44: VICVectCntl3 = 0x20 | 13; // use it for real-time clock
00000054 212D MOV R1,#0x2D
00000056 4800 LDR R0,=0xFFFFF20C
00000058 6001 STR R1,[R0,#0x0]
46: }
0000005A 4770 BX R14
0000005C ENDP ; 'init_clock?T'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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