cnt10.tan.qmsg

十进制加法计数器

{ "Info" "ITDB_TSU_RESULT" "CQI\[0\] ENA CLK 2.545 ns register " "Info: tsu for register \"CQI\[0\]\" (data pin = \"ENA\", clock pin = \"CLK\") is 2.545 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.458 ns + Longest pin register " "Info: + Longest pin to register delay is 5.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns ENA 1 PIN PIN_K14 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K14; Fanout = 4; PIN Node = 'ENA'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENA } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.705 ns) 5.458 ns CQI\[0\] 2 REG LC_X19_Y30_N2 6 " "Info: 2: + IC(3.666 ns) + CELL(0.705 ns) = 5.458 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.371 ns" { ENA CQI[0] } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns ( 32.83 % ) " "Info: Total cell delay = 1.792 ns ( 32.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.666 ns ( 67.17 % ) " "Info: Total interconnect delay = 3.666 ns ( 67.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.458 ns" { ENA CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.458 ns" { ENA ENA~out0 CQI[0] } { 0.000ns 0.000ns 3.666ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.923 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns CQI\[0\] 2 REG LC_X19_Y30_N2 6 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { CLK CQI[0] } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { CLK CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { CLK CLK~out0 CQI[0] } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.458 ns" { ENA CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.458 ns" { ENA ENA~out0 CQI[0] } { 0.000ns 0.000ns 3.666ns } { 0.000ns 1.087ns 0.705ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { CLK CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { CLK CLK~out0 CQI[0] } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK COUT CQI\[0\] 7.807 ns register " "Info: tco from clock \"CLK\" to destination pin \"COUT\" through register \"CQI\[0\]\" is 7.807 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.923 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns CQI\[0\] 2 REG LC_X19_Y30_N2 6 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { CLK CQI[0] } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { CLK CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { CLK CLK~out0 CQI[0] } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.728 ns + Longest register pin " "Info: + Longest register to pin delay is 4.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CQI\[0\] 1 REG LC_X19_Y30_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CQI[0] } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.366 ns) 1.206 ns Equal0~31 2 COMB LC_X19_Y30_N5 1 " "Info: 2: + IC(0.840 ns) + CELL(0.366 ns) = 1.206 ns; Loc. = LC_X19_Y30_N5; Fanout = 1; COMB Node = 'Equal0~31'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.206 ns" { CQI[0] Equal0~31 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(2.404 ns) 4.728 ns COUT 3 PIN PIN_M15 0 " "Info: 3: + IC(1.118 ns) + CELL(2.404 ns) = 4.728 ns; Loc. = PIN_M15; Fanout = 0; PIN Node = 'COUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.522 ns" { Equal0~31 COUT } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns ( 58.59 % ) " "Info: Total cell delay = 2.770 ns ( 58.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.958 ns ( 41.41 % ) " "Info: Total interconnect delay = 1.958 ns ( 41.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.728 ns" { CQI[0] Equal0~31 COUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.728 ns" { CQI[0] Equal0~31 COUT } { 0.000ns 0.840ns 1.118ns } { 0.000ns 0.366ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { CLK CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { CLK CLK~out0 CQI[0] } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.728 ns" { CQI[0] Equal0~31 COUT } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.728 ns" { CQI[0] Equal0~31 COUT } { 0.000ns 0.840ns 1.118ns } { 0.000ns 0.366ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "CQI\[0\] ENA CLK -2.435 ns register " "Info: th for register \"CQI\[0\]\" (data pin = \"ENA\", clock pin = \"CLK\") is -2.435 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.923 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.553 ns) + CELL(0.542 ns) 2.923 ns CQI\[0\] 2 REG LC_X19_Y30_N2 6 " "Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.095 ns" { CLK CQI[0] } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.87 % ) " "Info: Total cell delay = 1.370 ns ( 46.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.553 ns ( 53.13 % ) " "Info: Total interconnect delay = 1.553 ns ( 53.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { CLK CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { CLK CLK~out0 CQI[0] } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.458 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns ENA 1 PIN PIN_K14 4 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K14; Fanout = 4; PIN Node = 'ENA'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENA } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.705 ns) 5.458 ns CQI\[0\] 2 REG LC_X19_Y30_N2 6 " "Info: 2: + IC(3.666 ns) + CELL(0.705 ns) = 5.458 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.371 ns" { ENA CQI[0] } "NODE_NAME" } } { "CNT10.vhd" "" { Text "E:/CNT10B/CNT10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns ( 32.83 % ) " "Info: Total cell delay = 1.792 ns ( 32.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.666 ns ( 67.17 % ) " "Info: Total interconnect delay = 3.666 ns ( 67.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.458 ns" { ENA CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.458 ns" { ENA ENA~out0 CQI[0] } { 0.000ns 0.000ns 3.666ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.923 ns" { CLK CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.923 ns" { CLK CLK~out0 CQI[0] } { 0.000ns 0.000ns 1.553ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.458 ns" { ENA CQI[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.458 ns" { ENA ENA~out0 CQI[0] } { 0.000ns 0.000ns 3.666ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 15 10:07:47 2009 " "Info: Processing ended: Wed Apr 15 10:07:47 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}