cnt10.tan.rpt

十进制加法计数器

+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To     ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A   ; None         ; 2.545 ns   ; ENA  ; CQI[0] ; CLK      ;
; N/A   ; None         ; 2.545 ns   ; ENA  ; CQI[3] ; CLK      ;
; N/A   ; None         ; 2.545 ns   ; ENA  ; CQI[2] ; CLK      ;
; N/A   ; None         ; 2.545 ns   ; ENA  ; CQI[1] ; CLK      ;
+-------+--------------+------------+------+--------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+--------+---------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To      ; From Clock ;
+-------+--------------+------------+--------+---------+------------+
; N/A   ; None         ; 7.807 ns   ; CQI[0] ; COUT    ; CLK        ;
; N/A   ; None         ; 7.499 ns   ; CQI[3] ; COUT    ; CLK        ;
; N/A   ; None         ; 7.295 ns   ; CQI[1] ; COUT    ; CLK        ;
; N/A   ; None         ; 7.212 ns   ; CQI[2] ; COUT    ; CLK        ;
; N/A   ; None         ; 6.660 ns   ; CQI[0] ; OUTY[0] ; CLK        ;
; N/A   ; None         ; 6.651 ns   ; CQI[3] ; OUTY[3] ; CLK        ;
; N/A   ; None         ; 6.647 ns   ; CQI[2] ; OUTY[2] ; CLK        ;
; N/A   ; None         ; 6.647 ns   ; CQI[1] ; OUTY[1] ; CLK        ;
+-------+--------------+------------+--------+---------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -2.435 ns ; ENA  ; CQI[0] ; CLK      ;
; N/A           ; None        ; -2.435 ns ; ENA  ; CQI[3] ; CLK      ;
; N/A           ; None        ; -2.435 ns ; ENA  ; CQI[2] ; CLK      ;
; N/A           ; None        ; -2.435 ns ; ENA  ; CQI[1] ; CLK      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Apr 15 10:07:47 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CNT10 -c CNT10 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 422.12 MHz between source register "CQI[0]" and destination register "CQI[0]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.987 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
            Info: 2: + IC(0.448 ns) + CELL(0.539 ns) = 0.987 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
            Info: Total cell delay = 0.539 ns ( 54.61 % )
            Info: Total interconnect delay = 0.448 ns ( 45.39 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.923 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
                Info: Total cell delay = 1.370 ns ( 46.87 % )
                Info: Total interconnect delay = 1.553 ns ( 53.13 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.923 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
                Info: Total cell delay = 1.370 ns ( 46.87 % )
                Info: Total interconnect delay = 1.553 ns ( 53.13 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "CQI[0]" (data pin = "ENA", clock pin = "CLK") is 2.545 ns
    Info: + Longest pin to register delay is 5.458 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K14; Fanout = 4; PIN Node = 'ENA'
        Info: 2: + IC(3.666 ns) + CELL(0.705 ns) = 5.458 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 1.792 ns ( 32.83 % )
        Info: Total interconnect delay = 3.666 ns ( 67.17 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 1.370 ns ( 46.87 % )
        Info: Total interconnect delay = 1.553 ns ( 53.13 % )
Info: tco from clock "CLK" to destination pin "COUT" through register "CQI[0]" is 7.807 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 1.370 ns ( 46.87 % )
        Info: Total interconnect delay = 1.553 ns ( 53.13 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.728 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
        Info: 2: + IC(0.840 ns) + CELL(0.366 ns) = 1.206 ns; Loc. = LC_X19_Y30_N5; Fanout = 1; COMB Node = 'Equal0~31'
        Info: 3: + IC(1.118 ns) + CELL(2.404 ns) = 4.728 ns; Loc. = PIN_M15; Fanout = 0; PIN Node = 'COUT'
        Info: Total cell delay = 2.770 ns ( 58.59 % )
        Info: Total interconnect delay = 1.958 ns ( 41.41 % )
Info: th for register "CQI[0]" (data pin = "ENA", clock pin = "CLK") is -2.435 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 1.370 ns ( 46.87 % )
        Info: Total interconnect delay = 1.553 ns ( 53.13 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.458 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K14; Fanout = 4; PIN Node = 'ENA'
        Info: 2: + IC(3.666 ns) + CELL(0.705 ns) = 5.458 ns; Loc. = LC_X19_Y30_N2; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 1.792 ns ( 32.83 % )
        Info: Total interconnect delay = 3.666 ns ( 67.17 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Apr 15 10:07:47 2009
    Info: Elapsed time: 00:00:02