cnt10.vhd

十进制加法计数器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
   PORT (CLK,RST,ENA: IN STD_LOGIC;
                OUTY: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
               COUT: OUT STD_LOGIC);
END CNT10;
ARCHITECTURE behav OF CNT10 IS
BEGIN
  PROCESS(CLK ,RST, ENA)
   VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN 
    IF RST ='1' THEN  CQI :=(OTHERS =>'0');
     ELSIF CLK 'EVENT AND CLK ='1' THEN
     IF ENA='1' THEN
      IF CQI <9 THEN CQI := CQI +1;
        ELSE  CQI := (OTHERS => '0');
      END IF;
     END IF;
     END IF;

     IF CQI = 9 THEN COUT <='1';
       ELSE  COUT<='0';
      END IF;
       OUTY <= CQI;
   END PROCESS;
END behav;