cn.tan.qmsg

计数器和译码器的程序

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK0 " "Info: Assuming node \"CLOCK0\" is an undefined clock" {  } { { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 144 -8 160 160 "CLOCK0" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLOCK0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK0 register CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] register CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 98.04 MHz 10.2 ns Internal " "Info: Clock \"CLOCK0\" has Internal fmax of 98.04 MHz between source register \"CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]\" and destination register \"CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]\" (period= 10.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns + Longest register register " "Info: + Longest register to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 1 REG LC2 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 5.700 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 2 REG LC2 29 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 5.700 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 54.39 % ) " "Info: Total cell delay = 3.100 ns ( 54.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 45.61 % ) " "Info: Total interconnect delay = 2.600 ns ( 45.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK0 destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK0\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CLOCK0 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK0 } "NODE_NAME" } } { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 144 -8 160 160 "CLOCK0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 2 REG LC2 29 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK0 source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK0\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CLOCK0 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK0 } "NODE_NAME" } } { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 144 -8 160 160 "CLOCK0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 2 REG LC2 29 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 2.600ns } { 0.000ns 3.100ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] ENA0 CLOCK0 4.800 ns register " "Info: tsu for register \"CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]\" (data pin = \"ENA0\", clock pin = \"CLOCK0\") is 4.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns + Longest pin register " "Info: + Longest pin to register delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns ENA0 1 PIN PIN_85 4 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_85; Fanout = 4; PIN Node = 'ENA0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENA0 } "NODE_NAME" } } { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 176 -8 160 192 "ENA0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.300 ns) 5.300 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 2 REG LC2 29 " "Info: 2: + IC(2.600 ns) + CELL(1.300 ns) = 5.300 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { ENA0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.700 ns ( 50.94 % ) " "Info: Total cell delay = 2.700 ns ( 50.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 49.06 % ) " "Info: Total interconnect delay = 2.600 ns ( 49.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { ENA0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { ENA0 ENA0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 1.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK0 destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK0\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CLOCK0 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK0 } "NODE_NAME" } } { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 144 -8 160 160 "CLOCK0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 2 REG LC2 29 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { ENA0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { ENA0 ENA0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 1.300ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK0 LED\[0\] CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 13.600 ns register " "Info: tco from clock \"CLOCK0\" to destination pin \"LED\[0\]\" through register \"CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]\" is 13.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK0 source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK0\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns CLOCK0 1 CLK PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK0 } "NODE_NAME" } } { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 144 -8 160 160 "CLOCK0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 2 REG LC2 29 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\] 1 REG LC2 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst\|lpm_counter:CQI_rtl_0\|dffs\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 7.000 ns DECL7S:inst1\|Mux6~115 2 COMB LC11 1 " "Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 7.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'DECL7S:inst1\|Mux6~115'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] DECL7S:inst1|Mux6~115 } "NODE_NAME" } } { "old_DECL7S.vhd" "" { Text "E:/MY/old_DECL7S.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 8.600 ns LED\[0\] 3 PIN PIN_96 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.600 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'LED\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { DECL7S:inst1|Mux6~115 LED[0] } "NODE_NAME" } } { "CN.bdf" "" { Schematic "E:/MY/CN.bdf" { { 232 632 808 248 "LED\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 69.77 % ) " "Info: Total cell delay = 6.000 ns ( 69.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 30.23 % ) " "Info: Total interconnect delay = 2.600 ns ( 30.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.600 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] DECL7S:inst1|Mux6~115 LED[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.600 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] DECL7S:inst1|Mux6~115 LED[0] } { 0.000ns 2.600ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { CLOCK0 CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.400 ns" { CLOCK0 CLOCK0~out CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.600 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] DECL7S:inst1|Mux6~115 LED[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.600 ns" { CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] DECL7S:inst1|Mux6~115 LED[0] } { 0.000ns 2.600ns 0.000ns } { 0.000ns 4.400ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}