cn.tan.rpt

计数器和译码器的程序

+----------------------------------------------------------------------------------------------------+
; tco                                                                                                ;
+-------+--------------+------------+------------------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                                     ; To     ; From Clock ;
+-------+--------------+------------+------------------------------------------+--------+------------+
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[0] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[0] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[0] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[0] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[1] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[1] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[1] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[1] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[3] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[3] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[3] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[3] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[4] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[4] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[4] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[4] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[2] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[2] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[2] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[2] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[5] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[5] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[5] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[5] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; LED[6] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; LED[6] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; LED[6] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; LED[6] ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; COUT0  ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; COUT0  ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; COUT0  ; CLOCK0     ;
; N/A   ; None         ; 13.600 ns  ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; COUT0  ; CLOCK0     ;
+-------+--------------+------------+------------------------------------------+--------+------------+


+------------------------------------------------------------------------------------------------------+
; th                                                                                                   ;
+---------------+-------------+-----------+------+------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                       ; To Clock ;
+---------------+-------------+-----------+------+------------------------------------------+----------+
; N/A           ; None        ; -0.600 ns ; ENA0 ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0] ; CLOCK0   ;
; N/A           ; None        ; -0.600 ns ; ENA0 ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[3] ; CLOCK0   ;
; N/A           ; None        ; -0.600 ns ; ENA0 ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[2] ; CLOCK0   ;
; N/A           ; None        ; -0.600 ns ; ENA0 ; CNT10:inst|lpm_counter:CQI_rtl_0|dffs[1] ; CLOCK0   ;
+---------------+-------------+-----------+------+------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Apr 15 16:57:28 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CN -c CN
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK0" is an undefined clock
Info: Clock "CLOCK0" has Internal fmax of 98.04 MHz between source register "CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]" and destination register "CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]" (period= 10.2 ns)
    Info: + Longest register to register delay is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 5.700 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: Total cell delay = 3.100 ns ( 54.39 % )
        Info: Total interconnect delay = 2.600 ns ( 45.61 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLOCK0" to destination register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLOCK0" to source register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]" (data pin = "ENA0", clock pin = "CLOCK0") is 4.800 ns
    Info: + Longest pin to register delay is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_85; Fanout = 4; PIN Node = 'ENA0'
        Info: 2: + IC(2.600 ns) + CELL(1.300 ns) = 5.300 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: Total cell delay = 2.700 ns ( 50.94 % )
        Info: Total interconnect delay = 2.600 ns ( 49.06 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "CLOCK0" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: tco from clock "CLOCK0" to destination pin "LED[0]" through register "CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]" is 13.600 ns
    Info: + Longest clock path from clock "CLOCK0" to source register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 7.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'DECL7S:inst1|Mux6~115'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 8.600 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'LED[0]'
        Info: Total cell delay = 6.000 ns ( 69.77 % )
        Info: Total interconnect delay = 2.600 ns ( 30.23 % )
Info: th for register "CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]" (data pin = "ENA0", clock pin = "CLOCK0") is -0.600 ns
    Info: + Longest clock path from clock "CLOCK0" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 4; CLK Node = 'CLOCK0'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_85; Fanout = 4; PIN Node = 'ENA0'
        Info: 2: + IC(2.600 ns) + CELL(1.300 ns) = 5.300 ns; Loc. = LC2; Fanout = 29; REG Node = 'CNT10:inst|lpm_counter:CQI_rtl_0|dffs[0]'
        Info: Total cell delay = 2.700 ns ( 50.94 % )
        Info: Total interconnect delay = 2.600 ns ( 49.06 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Apr 15 16:57:29 2009
    Info: Elapsed time: 00:00:03