pulse8.tan.qmsg

此文件为EDA的8位分频器

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "PULSE8.vhd" "" { Text "E:/8位分频器/PULSE8.vhd" 5 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FULL " "Info: Detected ripple clock \"FULL\" as buffer" {  } { { "PULSE8.vhd" "" { Text "E:/8位分频器/PULSE8.vhd" 10 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FULL" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 register lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 76.92 MHz 13.0 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 76.92 MHz between source register \"lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8\" and destination register \"lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 1 REG LC1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 2 REG LC1 22 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 9 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PULSE8.vhd" "" { Text "E:/8位分频器/PULSE8.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 2 REG LC1 22 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 9 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PULSE8.vhd" "" { Text "E:/8位分频器/PULSE8.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 2 REG LC1 22 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.000 ns" { lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 D\[0\] CLK 11.000 ns register " "Info: tsu for register \"lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8\" (data pin = \"D\[0\]\", clock pin = \"CLK\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns D\[0\] 1 PIN PIN_81 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'D\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } } { "PULSE8.vhd" "" { Text "E:/8位分频器/PULSE8.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 2 REG LC1 22 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { D[0] lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { D[0] lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { D[0] D[0]~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 9 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PULSE8.vhd" "" { Text "E:/8位分频器/PULSE8.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8 2 REG LC1 22 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\\P_REG:CNT8\[0\]_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { D[0] lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { D[0] D[0]~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { CLK lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { CLK CLK~out lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}