pulse8.tan.rpt

此文件为EDA的8位分频器

+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 17.000 ns  ; FOUT~reg0 ; FOUT ; CLK        ;
+-------+--------------+------------+-----------+------+------------+


+---------------------------------------------------------------------------------------------------------------+
; th                                                                                                            ;
+---------------+-------------+-----------+------+---------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                                ; To Clock ;
+---------------+-------------+-----------+------+---------------------------------------------------+----------+
; N/A           ; None        ; -3.000 ns ; D[0] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[7] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[6] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[5] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[4] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[3] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[2] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6 ; CLK      ;
; N/A           ; None        ; -3.000 ns ; D[1] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7 ; CLK      ;
+---------------+-------------+-----------+------+---------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 28 13:30:14 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PULSE8 -c PULSE8
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "FULL" as buffer
Info: Clock "CLK" has Internal fmax of 76.92 MHz between source register "lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8" and destination register "lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8" (data pin = "D[0]", clock pin = "CLK") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'D[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "CLK" to destination pin "FOUT" through register "FOUT~reg0" is 17.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 12.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC10; Fanout = 1; REG Node = 'FULL'
        Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'FOUT~reg0'
        Info: Total cell delay = 10.000 ns ( 83.33 % )
        Info: Total interconnect delay = 2.000 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 2; REG Node = 'FOUT~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'FOUT'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8" (data pin = "D[0]", clock pin = "CLK") is -3.000 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'D[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC1; Fanout = 22; REG Node = 'lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Tue Apr 28 13:30:15 2009
    Info: Elapsed time: 00:00:02