📄 pulse8.fit.rpt
字号:
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; CLK ; PIN_83 ; 9 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+-------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+---------------------------------------------------+---------+
; Name ; Fan-Out ;
+---------------------------------------------------+---------+
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7 ; 9 ;
; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 ; 9 ;
; D[7] ; 1 ;
; D[6] ; 1 ;
; D[5] ; 1 ;
; D[4] ; 1 ;
; D[3] ; 1 ;
; D[2] ; 1 ;
; D[1] ; 1 ;
; D[0] ; 1 ;
; FOUT~reg0 ; 1 ;
; FULL ; 1 ;
+---------------------------------------------------+---------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 17 / 288 ( 6 % ) ;
; PIAs ; 17 / 288 ( 6 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 2.13) ; Number of LABs (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 1.25) ; Number of LABs (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0 ; 7 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC1 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, D[0] ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC2 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, D[1], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC4 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, D[2], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC5 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, D[3], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC6 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, D[4], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC7 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, D[5], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC8 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, D[6], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC9 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, D[7], lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1 ; lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, FULL ;
; A ; LC10 ; CLK, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|1, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|2, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|8, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|3, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|4, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|5, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|6, lpm_counter:\P_REG:CNT8[0]_rtl_0|p8count:p8c[0]|7 ; FOUT~reg0 ;
; A ; LC3 ; FULL ; FOUT ;
+-----+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Apr 28 13:30:06 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off PULSE8 -c PULSE8
Info: Selected device EPM7128SLC84-15 for design "PULSE8"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Apr 28 13:30:06 2009
Info: Elapsed time: 00:00:02
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -