modbus_reg.h.svn-base

给MOTO 360 单片机 开发的MODBUS协议 直流奥特寻协议。。要用SDS编译

#define PC_CTS1		((WORD)0x0010)
#define PC_CD1		((WORD)0x0020)
#define PC_CTS2		((WORD)0x0040)
#define PC_CD2		((WORD)0x0080)
#define PC_CTS3		((WORD)0x0100)
#define PC_CD3		((WORD)0x0200)
#define PC_CTS4		((WORD)0x0400)
#define PC_CD4		((WORD)0x0800)

//**************************************************************************************************************
#define MBAR        0x0003ff00                   //MBAR:module base address register
#define DPRBASE     0x00200000
#define VECTOR_BASE 0x00400000                   //Set in the vector base register
#define REGB        DPRBASE+0x1000

#define SCC1_BASE   DPRBASE+0x0c00               //SCC1_BASE=DPRBASE+0x0c00
#define SCC2_BASE   DPRBASE+0x0d00               //SCC2_BASE=DPRBASE+0x0d00
#define SCC3_BASE   DPRBASE+0x0e00               //SCC3_BASE=DPRBASE+0x0e00
#define SCC4_BASE   DPRBASE+0x0f00               //SCC4_BASE=DPRBASE+0x0f00

#define VECTOR_TAB ((volatile void **)(VECTOR_BASE))    //the Vector Table
//volatile void * VECTOR_BASE[256] _at_ VECTOR_BASE;

#define DPRAM ((volatile BYTE *)(DPRBASE))

#define MCR   (*((volatile DWORD *)(REGB+0x0000)))    //MCR:module configuration register
#define SYPCR (*((volatile BYTE *)(REGB+0x0022)))    //SYPCR:system protection control

#define GMR   (*((volatile DWORD *)(REGB+0x0040)))     //GMR:global memory register

#define BR0   (*((volatile DWORD *)(REGB+0x0050)))     //BR0:base register 0
#define OR0   (*((volatile DWORD *)(REGB+0x0054)))     //OR0:option register 0

#define BR1   (*((volatile DWORD *)(REGB+0x0060)))     //BR1:base register 1
#define OR1   (*((volatile DWORD *)(REGB+0x0064)))     //OR1:option register 1

#define BR2   (*((volatile DWORD *)(REGB+0x0070)))     //BR2:base register 2
#define OR2   (*((volatile DWORD *)(REGB+0x0074)))     //OR2:option register 2

#define CLKOCR  (*((volatile BYTE  *)(REGB+0x000c)))  //CLKOCR:clko control register
#define PLLCR   (*((volatile WORD *)(REGB+0x0010)))  //PLLCR:PLL control register
#define CDVCR   (*((volatile WORD *)(REGB+0x0014)))  //CDVCR:clock divider control register
#define SICR    (*((volatile DWORD  *)(REGB+0x06ec)))  //SICR:SI clock route
#define PEPAR   (*((volatile WORD *)(REGB+0x0016)))  //PEPAR:port E pin assignment register

#define PICR	(*((volatile WORD *)(REGB+0x0026)))  //Periodic Interrupt Control Register
#define PITR	(*((volatile WORD *)(REGB+0x002A)))  //Periodic Interrupt Timing Register


//*******************************************************************************************
//QUICC CPM register memory map
//*******************************************************************************************
#define SDCR  (*((volatile WORD *)(REGB+0x051e)))     //SDCR:SDMA configuration register

#define PADIR (*((volatile WORD *)(REGB+0x0550)))    //PADIR:port A data direction register
#define PAPAR (*((volatile WORD *)(REGB+0x0552)))    //PAPAR:port A pin assignment register
#define PAODR (*((volatile WORD *)(REGB+0x0554)))    //PAODR:port A open drain register
#define PADAT (*((volatile WORD *)(REGB+0x0556)))    //PADAT:port A data register

#define PBDIR (*((volatile DWORD*)(REGB+0x06b8)))     //PADIR:port B data direction register
#define PBPAR (*((volatile DWORD*)(REGB+0x06bc)))     //PAPAR:port B pin assignment register
#define PBODR (*((volatile WORD *)(REGB+0x06c2)))    //PAODR:port B open drain register
#define PBDAT (*((volatile DWORD*)(REGB+0x06c4)))     //PADAT:port B data register

#define PCDIR (*((volatile WORD *)(REGB+0x0560)))    //PCDIR:port C data direction register
#define PCPAR (*((volatile WORD *)(REGB+0x0562)))    //PCPAR:port C pin assignment register
#define PCSO  (*((volatile WORD *)(REGB+0x0564)))    //PCSO: port C special options
#define PCDAT (*((volatile WORD *)(REGB+0x0566)))    //PCDAT:port C data register

#define CR    (*((volatile WORD *)(REGB+0x05c0)))    //CR:command register

#define RCCR  (*((volatile WORD *)(REGB+0x05c4)))    //RCCR:risc configuration register

#define CPCR1 (*((volatile WORD *)(REGB+0x05CC)))    //CPCR1:CP Control Register 1
#define CPCR2 (*((volatile WORD *)(REGB+0x05CE)))    //CPCR2:CP Control Register 2

#define RTER  (*((volatile WORD *)(REGB+0x05D6)))    //RISC Timers Event Register, A bit is cleared by writing a one
#define RTMR  (*((volatile WORD *)(REGB+0x05DA)))    //RISC Timers Mask Register, read/write

#define CICR  (*((volatile DWORD  *)(REGB+0x0540)))    //CICR:CP interrupt configuration register
#define CIPR  (*((volatile DWORD  *)(REGB+0x0544)))    //CIPR:CP Interrupt Pending Register
#define CIMR  (*((volatile DWORD  *)(REGB+0x0548)))    //CIMR:CP interrupt mask register
#define CISR  (*((volatile DWORD  *)(REGB+0x054C)))    //CISR:CP In-Service Register

#define TGCR  (*((volatile WORD *)(REGB + 0x580)))   //Timer Global Configuration Register 0000 H TIMER
#define TMR1  (*((volatile WORD *)(REGB + 0x590)))   //Timer1 Mode Register 0000
#define TMR2  (*((volatile WORD *)(REGB + 0x592)))   //Timer2 Mode Register 0000
#define TRR1  (*((volatile WORD *)(REGB + 0x594)))   //Timer1 Reference Register FFFF
#define TRR2  (*((volatile WORD *)(REGB + 0x596)))   //Timer2 Reference Register FFFF
#define TCR1  (*((volatile WORD *)(REGB + 0x598)))   //Timer1 Capture Register 0000
#define TCR2  (*((volatile WORD *)(REGB + 0x59A)))   //Timer2 Capture Register 0000
#define TCN1  (*((volatile WORD *)(REGB + 0x59C)))   //Timer1 Counter 0000
#define TCN2  (*((volatile WORD *)(REGB + 0x59E)))   //Timer2 Counter 0000
#define TMR3  (*((volatile WORD *)(REGB + 0x5A0)))   //Timer3 Mode Register 0000
#define TMR4  (*((volatile WORD *)(REGB + 0x5A2)))   //Timer4 Mode Register 0000
#define TRR3  (*((volatile WORD *)(REGB + 0x5A4)))   //Timer3 Reference Register FFFF
#define TRR4  (*((volatile WORD *)(REGB + 0x5A6)))   //Timer4 Reference Register FFFF
#define TCR3  (*((volatile WORD *)(REGB + 0x5A8)))   //Timer3 Capture Register 0000
#define TCR4  (*((volatile WORD *)(REGB + 0x5AA)))   //Timer4 Capture Register 0000
#define TCN3  (*((volatile WORD *)(REGB + 0x5AC)))   //Timer3 Counter 0000
#define TCN4  (*((volatile WORD *)(REGB + 0x5AE)))   //Timer4 Counter 0000
#define TER1  (*((volatile WORD *)(REGB + 0x5B0)))   //Timer1 Event Register 0000
#define TER2  (*((volatile WORD *)(REGB + 0x5B2)))   //Timer2 Event Register 0000
#define TER3  (*((volatile WORD *)(REGB + 0x5B4)))   //Timer3 Event Register 0000
#define TER4  (*((volatile WORD *)(REGB + 0x5B6)))   //Timer4 Event Register 0000


#define BRGC1 (*((volatile DWORD  *)(REGB+0x05f0)))    //BRGC1:
#define BRGC2 (*((volatile DWORD  *)(REGB+0x05f4)))    //BRGC2:
#define BRGC3 (*((volatile DWORD  *)(REGB+0x05f8)))    //BRGC3:
#define BRGC4 (*((volatile DWORD  *)(REGB+0x05fc)))    //BRGC4:
//******************************************************************************************
typedef struct RX_BD_ST{                      //UART
    unsigned Empty: 1;
    unsigned :  1;
    unsigned Wrap:  1;
    unsigned Interrupt: 1;
    unsigned C: 1;        //Control character
    unsigned A: 1;        //Address                                                
    unsigned CM : 1;      //Continuous mode
    unsigned ID : 1;      //ID: Buffer Closed on Reception of IDLE (bit 6)
    //The buffer was closed due to the reception of an IDLE in the middle of a frame.
    unsigned AM : 1;      //Address match
    unsigned    : 1; 
    unsigned BR : 1;      //BR: break received                                            
    unsigned FR : 1;      //FR: Framing Error 
    //A character with a parity error was received.
    unsigned PR : 1;      //PR: Parity error 
    unsigned    : 1;                      
    unsigned OV : 1;      //OV - Overrun (bit 1)
    //A receiver overrun occurred during frame reception.
    unsigned CD : 1;      //CD - Carrier Detect lost (bit 0)
    //The Carrier Detect signal was negated during frame reception.
};
/*	                   
typedef struct TX_BD_ST{                        //UART
unsigned Ready: 1;
unsigned :      1;
unsigned Wrap:  1;
unsigned Interrupt: 1;
unsigned CR: 1;
unsigned A:         1;         //Address 
unsigned CM :       1;         //Continuous mode	
unsigned Preamble:  1;
//0 = No preamble sequence is sent.
//1 = A preamble sequence is send before the data. The length of the
//preamble sequence is determined by IDLEC.	
unsigned NS :1;         //NS:no stop bit transmitted	                      
unsigned :   6;
unsigned CT :1;         //CTS lost (bit 0)
//0 = The CTS signal remained asserted during transmission.
//1 = The CTS signal was negated during transmission.
};    */

typedef struct TX_BD_ST{
    unsigned Ready: 1;
    unsigned :1;
    unsigned Wrap:  1;
    unsigned Interrupt: 1;
    unsigned CTSR: 1;     //CR:clear to send report
    unsigned A: 1;     //TC:Transmit Check Sum
    //0 = Close the buffer after the last data byte.
    //1 = Transmit the Check Sum after the last byte of data. After the Check
    //Sum, transmit the End Delimiter (ED).
    unsigned CM:1;
    unsigned Preamble: 1;
    //0 = No preamble sequence is sent.
    //1 = A preamble sequence is send before the data. The length of the
    //preamble sequence is determined by IDLEC.
    unsigned NS: 1;
    unsigned :   6;     //Slot Timer Start (bit 4)
    //0 = Do not start slot timer at the end of frame.
    //1 = Start slot timer at the end of frame.
    unsigned CT: 1;     //CTS lost (bit 0)
    //0 = The CTS signal remained asserted during transmission.
    //1 = The CTS signal was negated during transmission.
};	                    

typedef struct GSMR_L{
    unsigned :     14;
    unsigned TCDR:  2;
    unsigned RDCR:  2;
    //00 = 1′ clock mode (Only NRZ or NRZI encodings are allowed.)
    //01 = 8′ clock mode
    //10 = 16′ clock mode (normally chosen for UART and AppleTalk)
    //11 = 32′ clock mode
    unsigned :      6;
    unsigned DIAG:  2;	  //01 =Local loopback mode
    unsigned ENR:   1;
    unsigned ENT:   1;
    unsigned MODE:  4;    //UART:0100
};
typedef struct PSMR{
    unsigned FLC:   1;    //FLC - Flow control (bit 15)
    //0 = Normal operation.
    //1 = Asynchronous flow control.

    unsigned SL:    1;    //SL - Stop Length (bit 14)
    //0 = One stop bit.
    //1 = Two stop bits.

    unsigned CL:    2;    //CL - Character Length
    //00 = 5 Data Bits
    //01 = 6 Data Bits
    //10 = 7 Data Bits
    //11 = 8 Data Bits

    unsigned UM:    2;    //UM - UART Mode
    //00 = Normal operation
    unsigned FRZ:   1;    //FRZ - freeze transmission
    //0 = Normal operation.Restart from where stoped.
    //1 = Restart with the next character
    unsigned RZS:   1;    //RZS - Receive zero stop bits.
    //0 = Normal operation.
    //1 = Receive data without stop bits.                     	                    
    unsigned SYN:   1;    //SYN - Synchronous Mode (bit 7)
    //0 = Normal asynchronous operation.
    //1 = Synchronous operation.
    unsigned DRT:   1;    //DRT - Disable receiver while transmitting (bit 6)
    //0 = Normal operation.
    //1 = Disable receiver while transmitting.
    unsigned :      1;
    unsigned PEN:   1;    //PEN - Parity Enable (bit 4)
    //0 = No parity.
    //1 = Parity enabled.