modbus_reg.h.svn-base

给MOTO 360 单片机 开发的MODBUS协议 直流奥特寻协议。。要用SDS编译

/*******************************************************************************************
* MC68360 Command & Configuration register for ProfiBus
* Coded by ZhangTao
* 2006/8/19
*******************************************************************************************/
#ifndef _M68360_MODBUSREG_H_
#define _M68360_MODBUSREG_H_

#ifndef BYTE
#define BYTE 	unsigned char
#define WORD 	unsigned short
#define DWORD	unsigned long
#endif

/* CPM Command register masks: */
#define CPM_CR_RST	    ((WORD)0x8000)
#define CPM_CR_OPCODE	  ((WORD)0x0f00)
#define CPM_CR_CHAN	    ((WORD)0x00f0)
#define CPM_CR_FLG      ((WORD)0x0001)

/* CPM Command set (opcodes): */
#define INIT_TRX_PARAMS	((WORD)0x0000)    //For: SCC SMC (UART/Trans) SMC (GCI) SPI
#define INIT_RX_PARAMS	((WORD)0x0100)    //For: SCC SMC (UART/Trans) SPI
#define INIT_TX_PARAMS	((WORD)0x0200)    //For: SCC SMC (UART/Trans) SPI
#define HUNT_MODE       ((WORD)0x0300)    //For: SCC SMC (UART/Trans)
#define STOP_TX         ((WORD)0x0400)    //For: SCC SMC (UART/Trans)
#define GRSTOP_TX       ((WORD)0x0500)    //For: SCC
#define INIT_IDMA       ((WORD)0x0500)    //For: IDMA
#define RESTART_TX      ((WORD)0x0600)    //For: SCC SMC (UART/Trans)
#define CLOSE_RXBD      ((WORD)0x0700)    //For: SCC SMC (UART/Trans) SPI
#define SET_GADDR       ((WORD)0x0800)    //For: SCC
#define SET_TIMER       ((WORD)0x0800)    //For: RISC TIMER
#define GCI_TIMEOUT     ((WORD)0x0900)    //For: SMC (GCI)
#define GCI_ABORT       ((WORD)0x0a00)    //For: SMC (GCI)
#define RESET_BCS       ((WORD)0x0a00)    //For: SCC

/* CPM Channel numbers. */
#define CPM_CR_CH_SCC1	((WORD)0x0000)
#define CPM_CR_CH_SCC2	((WORD)0x0040)
#define CPM_CR_CH_SPI	((WORD)0x0050)	/* SPI / RISC Timers */
#define CPM_CR_CH_TMR	((WORD)0x0050)
#define CPM_CR_CH_SCC3	((WORD)0x0080)
#define CPM_CR_CH_SMC1	((WORD)0x0090)	/* SMC1 / IDMA1 */
#define CPM_CR_CH_IDMA1	((WORD)0x0090)
#define CPM_CR_CH_SCC4	((WORD)0x00c0)
#define CPM_CR_CH_SMC2	((WORD)0x00d0)	/* SMC2 / IDMA2 */
#define CPM_CR_CH_IDMA2	((WORD)0x00d0)

#define cr_cmd(CMD, CH)	( CMD | CH )

/* CPM Interrupt Mask Register CIMR*/

#define CIMR_PC15		0x80000000	/* Parallel I/O Port C[15] */
#define CIMR_SCC1		0x40000000	/* SCC 1 */
#define CIMR_SCC2		0x20000000	/* SCC 2 */
#define CIMR_SCC3		0x10000000	/* SCC 3 */
#define CIMR_SCC4		0x08000000	/* SCC 4 */
#define CIMR_PC14		0x04000000	/* Parallel I/O Port C[14] */
#define CIMR_TIMER1		0x02000000	/* Timer 1 */
#define CIMR_PC13		0x01000000	/* Parallel I/O Port C[13] */
#define CIMR_PC12		0x00800000	/* Parallel I/O Port C[12] */
#define CIMR_SDMA		0x00400000	/* SDMA bus error */
#define CIMR_IDMA1		0x00200000	/* IDMA 1 */
#define CIMR_IDMA2		0x00100000	/* IDMA 2 */
#define CIMR_TIMER2		0x00040000	/* Timer 2 */
#define CIMR_R_TT		0x00020000	/* Risc Timer Table */
#define CIMR_I2C		0x00010000	/* I2C */
#define CIMR_PC11		0x00008000	/* Parallel I/O Port C[11] */
#define CIMR_PC10		0x00004000	/* Parallel I/O Port C[10] */
#define CIMR_TIMER3		0x00001000	/* Timer 3 */
#define CIMR_PC9		0x00000800	/* Parallel I/O Port C[9] */
#define CIMR_PC8		0x00000400	/* Parallel I/O Port C[8] */
#define CIMR_PC7		0x00000200	/* Parallel I/O Port C[7] */
#define CIMR_TIMER4		0x00000080	/* Timer 4 */
#define CIMR_PC6		0x00000040	/* Parallel I/O Port C[6] */
#define CIMR_SPI		0x00000020	/* SPI */
#define CIMR_SMC1		0x00000010	/* SMC 1 */
#define CIMR_SMC2_PIP	0x00000008	/* SMC 1 */
#define CIMR_PC5		0x00000004	/* Parallel I/O Port C[5] */
#define CIMR_PC4		0x00000002	/* Parallel I/O Port C[4] */
#define CIMR_ALL		0xfff7defe	/* all interrupt masks */

/* CPM Interrupt configuration Register CICR*/

#define CICR_SCCDP_MSK		0xc00000	/* SCCd Priority Order Mask */
#define CICR_SCCDP_SCC1		0x000000	/* SCC1 asserts the SCCd */
#define CICR_SCCDP_SCC2		0x400000	/* SCC2 asserts the SCCd */
#define CICR_SCCDP_SCC3		0x800000	/* SCC3 asserts the SCCd */
#define CICR_SCCDP_SCC4		0xc00000	/* SCC4 asserts the SCCd */
#define CICR_SCCCP_MSK		0x300000	/* SCCc Priority Order Mask */
#define CICR_SCCCP_SCC1		0x000000	/* SCC1 asserts the SCCc */
#define CICR_SCCCP_SCC2		0x100000	/* SCC2 asserts the SCCc */
#define CICR_SCCCP_SCC3		0x200000	/* SCC3 asserts the SCCc */
#define CICR_SCCCP_SCC4		0x300000	/* SCC4 asserts the SCCc */
#define CICR_SCCBP_MSK		0x0c0000	/* SCCb Priority Order Mask */
#define CICR_SCCBP_SCC1		0x000000	/* SCC1 asserts the SCCb */
#define CICR_SCCBP_SCC2		0x040000	/* SCC2 asserts the SCCb */
#define CICR_SCCBP_SCC3		0x080000	/* SCC3 asserts the SCCb */
#define CICR_SCCBP_SCC4		0x0c0000	/* SCC4 asserts the SCCb */
#define CICR_SCCAP_MSK		0x030000	/* SCCa Priority Order Mask */
#define CICR_SCCAP_SCC1		0x000000	/* SCC1 asserts the SCCa */
#define CICR_SCCAP_SCC2		0x010000	/* SCC2 asserts the SCCa */
#define CICR_SCCAP_SCC3		0x020000	/* SCC3 asserts the SCCa */
#define CICR_SCCAP_SCC4		0x030000	/* SCC4 asserts the SCCa */
#define CICR_IRL_MSK		0x00e000	/* Interrupt Request Level */
#define CICR_IRL_LVL0		0x000000	/* Interrupt Request Level 0 */
#define CICR_IRL_LVL1		0x002000	/* Interrupt Request Level 1 */
#define CICR_IRL_LVL2		0x004000	/* Interrupt Request Level 2 */
#define CICR_IRL_LVL3		0x006000	/* Interrupt Request Level 3 */
#define CICR_IRL_LVL4		0x008000	/* Interrupt Request Level 4 */
#define CICR_IRL_LVL5		0x00a000	/* Interrupt Request Level 5 */
#define CICR_IRL_LVL6		0x00c000	/* Interrupt Request Level 6 */
#define CICR_IRL_LVL7		0x00e000	/* Interrupt Request Level 7 */
#define CICR_HP_MASK		    0x001f00	/* Highest Priority */
#define CICR_IEN		    0x000080	/* Interrupt Enable */
#define CICR_SPS		    0x000001	/* Spread Priority Scheme */

/* CPM Interrupt in Service Register CISR*/

#define CISR_PC15		0x80000000	/* Parallel I/O Port C[15] */
#define CISR_SCC1		0x40000000	/* SCC 1 */
#define CISR_SCC2		0x20000000	/* SCC 2 */
#define CISR_SCC3		0x10000000	/* SCC 3 */
#define CISR_SCC4		0x08000000	/* SCC 4 */
#define CISR_PC14		0x04000000	/* Parallel I/O Port C[14] */
#define CISR_TIMER1		0x02000000	/* Timer 1 */
#define CISR_PC13		0x01000000	/* Parallel I/O Port C[13] */
#define CISR_PC12		0x00800000	/* Parallel I/O Port C[12] */
#define CISR_SDMA		0x00400000	/* SDMA bus error */
#define CISR_IDMA1		0x00200000	/* IDMA 1 */
#define CISR_IDMA2		0x00100000	/* IDMA 2 */
#define CISR_TIMER2		0x00040000	/* Timer 2 */
#define CISR_R_TT		0x00020000	/* Risc Timer Table */
#define CISR_I2C		0x00010000	/* I2C */
#define CISR_PC11		0x00008000	/* Parallel I/O Port C[11] */
#define CISR_PC10		0x00004000	/* Parallel I/O Port C[10] */
#define CISR_TIMER3		0x00001000	/* Timer 3 */
#define CISR_PC9		0x00000800	/* Parallel I/O Port C[9] */
#define CISR_PC8		0x00000400	/* Parallel I/O Port C[8] */
#define CISR_PC7		0x00000200	/* Parallel I/O Port C[7] */
#define CISR_TIMER4		0x00000080	/* Timer 4 */
#define CISR_PC6		0x00000040	/* Parallel I/O Port C[6] */
#define CISR_SPI		0x00000020	/* SPI */
#define CISR_SMC1		0x00000010	/* SMC 1 */
#define CISR_SMC2_PIP	0x00000008	/* SMC 1 */
#define CISR_PC5		0x00000004	/* Parallel I/O Port C[5] */
#define CISR_PC4		0x00000002	/* Parallel I/O Port C[4] */

#define CPM_INTERRUPT	6 
/* see MC68360 User's Manual, p. 7-377  */
#define CPM_VECTOR_BASE  0x04           /* 3 MSbits of CPM vector */

/*****************************************************************
CPM Interrupt vector encodings (MC68360UM p. 7-376)
*****************************************************************/
#define CPMVEC_NR           32
#define CPMVEC_PIO_PC0		0x1f
#define CPMVEC_SCC1		    0x1e
#define CPMVEC_SCC2		    0x1d
#define CPMVEC_SCC3	        0x1c
#define CPMVEC_SCC4	        0x1b
#define CPMVEC_PIO_PC1		0x1a
#define CPMVEC_TIMER1		0x19
#define CPMVEC_PIO_PC2		0x18
#define CPMVEC_PIO_PC3		0x17
#define CPMVEC_SDMA_CB_ERR	0x16
#define CPMVEC_IDMA1		0x15
#define CPMVEC_IDMA2		0x14
#define CPMVEC_RESERVED3	0x13
#define CPMVEC_TIMER2		0x12
#define CPMVEC_RISCTIMER	0x11
#define CPMVEC_RESERVED2	0x10
#define CPMVEC_PIO_PC4		0x0f
#define CPMVEC_PIO_PC5		0x0e
#define CPMVEC_TIMER3		0x0c
#define CPMVEC_PIO_PC6		0x0b
#define CPMVEC_PIO_PC7		0x0a
#define CPMVEC_PIO_PC8		0x09
#define CPMVEC_RESERVED1	0x08
#define CPMVEC_TIMER4		0x07
#define CPMVEC_PIO_PC9		0x06
#define CPMVEC_SPI		    0x05
#define CPMVEC_SMC1		    0x04
#define CPMVEC_SMC2		    0x03
#define CPMVEC_PIO_PC10		0x02
#define CPMVEC_PIO_PC11		0x01
#define CPMVEC_ERROR		0x00

/*****************************************************************
*        PIO control registers
*****************************************************************/
/* Port A - See 360UM p. 7-358
*
*  Note that most of these pins have alternate functions
*/

/* The macros are nice, but there are all sorts of references to 1-indexed
* facilities on the 68360... */
/* #define PA_RXD(n)	((WORD)(0x01<<(2*n))) */
/* #define PA_TXD(n)	((WORD)(0x02<<(2*n))) */
#define PA_RXD1		((WORD)0x0001)
#define PA_TXD1		((WORD)0x0002)
#define PA_RXD2		((WORD)0x0004)
#define PA_TXD2		((WORD)0x0008)
#define PA_RXD3		((WORD)0x0010)
#define PA_TXD3		((WORD)0x0020)
#define PA_RXD4		((WORD)0x0040)
#define PA_TXD4		((WORD)0x0080)
#define PA_CLK1		((WORD)0x0100)
#define PA_CLK2		((WORD)0x0200)
#define PA_CLK3		((WORD)0x0400)
#define PA_CLK4		((WORD)0x0800)
#define PA_CLK5		((WORD)0x1000)
#define PA_CLK6		((WORD)0x2000)
#define PA_CLK7		((WORD)0x4000)
#define PA_CLK8		((WORD)0x8000)

/* Port B - See 360UM p. 7-362
*/

/* Port C - See 360UM p. 7-365
*/
#define PC_RTS1		((WORD)0x0001)
#define PC_RTS2		((WORD)0x0002)
#define PC__RTS3	((WORD)0x0004) /* !RTS3 */
#define PC__RTS4	((WORD)0x0008) /* !RTS4 */