📄 modbusfdl.c.svn-base
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/*******************************************************************************************
* MODBUS Master/Slaver Module (For Test)
* Coded by XUWANSU
* 2007/6/26
*******************************************************************************************/
#include "MODBUS_REG.h"
#include "DPRam.h"
#include "modbus.h"
#include "console.h"
#include "dc_aotexun.h"
const unsigned long BRGC_code[5]={0x00010272,0x00010136,0x0001009A,0x00010032,0x00010018}; //for 24M
//24M
//311 4800 0x00010272
//155 9600 0x00010136
//77 19200 0x0001009A
//25 57600 0x00010032
//12 115200 0x00010018
volatile unsigned char SCC_TBUF[4][256],SCC_RBUF[4][256];
volatile unsigned char SCC_BAUD[4];
volatile unsigned char SCC_MS[4]; //1:master;0:slave
volatile unsigned char SCC_STNO[4]; //从站编号
volatile unsigned char SCC_PARITY[4]; //效验
volatile unsigned short SCC_PAUSE_TICKS[4]; //实际时间
volatile unsigned char SCC_TASKNO[4]; //task number
//volatile unsigned char SCC_MADDR_DC[4]; //DC设备主站地址
volatile unsigned char SCC_INTFLAG[4];
volatile unsigned char com_led;
/*******************************************************************************************/
void Init_SCCs_Config();
void Init_SCC1_Config();
void Init_SCC2_Config();
void Init_SCC3_Config();
void Init_SCC4_Config();
void Init_SCC1_Buff();
void Init_SCC2_Buff();
void Init_SCC3_Buff();
void Init_SCC4_Buff();
void SCC1_TxDATA(unsigned char Len,unsigned char *s);
void SCC2_TxDATA(unsigned char Len,unsigned char *s);
void SCC3_TxDATA(unsigned char Len,unsigned char *s);
void SCC4_TxDATA(unsigned char Len,unsigned char *s);
void SCC2_Tx_char(unsigned char s);
void Init_CPM();
void Init_CPM_Interrupt();
void cpm_error_interrupt();
void cpm_other_error();
void SCC1_IntProcess();
void SCC2_IntProcess();
void SCC3_IntProcess();
void SCC4_IntProcess();
void Timer1_IntProcess();
void Timer2_IntProcess();
void inittimer1();
void inittimer2();
void memsetchar ( unsigned char *s1, unsigned char ch, unsigned short n );
/*******************************************************************************************/
void Init_CPM()
{
//memsetchar((DPRAM+0xc00),0x00,512); //Clear Entire Dual-Port RAM
RCCR=0x0000;
CR=CPM_CR_RST|CPM_CR_FLG;
while(CR & CPM_CR_FLG);
CIMR=0x00000000; //清所有中断
}
void Init_CPM_Interrupt()
{
int ii;
CICR=
(CICR_SCCDP_SCC4 | CICR_SCCCP_SCC3 | CICR_SCCBP_SCC2 | CICR_SCCAP_SCC1) |
(CPM_INTERRUPT << 13) |
CICR_HP_MASK |
(CPM_VECTOR_BASE << 5) |
CICR_SPS;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_ERROR]=(void*)cpm_error_interrupt;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_SCC1]=(void*)SCC1_IntProcess;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_SCC2]=(void*)SCC2_IntProcess;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_SCC3]=(void*)SCC3_IntProcess;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_SCC4]=(void*)SCC4_IntProcess;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_TIMER1]=(void*)Timer1_IntProcess;
VECTOR_TAB[(CPM_VECTOR_BASE << 5)|CPMVEC_TIMER2]=(void*)Timer2_IntProcess;
CIMR=0x00000000;
CISR=0xFFF6DEFE; //Enable all interrupts
CIMR=CIMR_SCC1|CIMR_SCC2|CIMR_SCC4|CIMR_SCC3|CIMR_TIMER1|CIMR_TIMER2;
SCCM1=0x0005; //8:IDL--由IDL转到data或有data转到IDL,3:BUSY,1:RX
//68302:BRK,BUSY,RX
SCCM2=0x0005;
SCCM3=0x0005;
SCCM4=0x0005;
for (ii=0;ii<4;ii++)
{
SCC_INTFLAG[ii]=0;
}
((struct GSMR_L*)(&GSMR_L1))->ENR=1;
((struct GSMR_L*)(&GSMR_L2))->ENR=1;
((struct GSMR_L*)(&GSMR_L3))->ENR=1;
((struct GSMR_L*)(&GSMR_L4))->ENR=1;
}
void Init_SCCs_Config()
{
SDCR=0x0740; //SDMA configuration register,SDMA:serial direct memory access
PAPAR=0x55ff; //TXD1,RXD1,TXD2,RXD2,TXD3,RXD3,TXD4,RXD4 enable,对应PA0-7
PADIR=0x0000; //init input and output of RXD and TXD
PAODR=0x0000; //the i/o pin is actively driven as an output
PBPAR=0x00FC0; //对应PB12-15,标准输出口
PBDIR=0x0f021;
PBODR=0x001E;
PBDAT=0xF000;
PCPAR=0x000F;
PCDIR=0x0000;
PCSO=0x0000; //Configure no modem,7-369 !!!EXTx
SICR=0x1b120900;
//00011011000100100000100100000000 //SCCx receive and transmit clock is BRGx (x=1~4)
Init_SCC1_Buff();
Init_SCC2_Buff();
Init_SCC3_Buff();
Init_SCC4_Buff();
}
void Init_SCC1_Buff()
{
SCC1_TX_BD0_ST=0x2000;
SCC1_TX_BD0_LN=0;
SCC1_TX_BD0_PT=(long)SCC_TBUF[0];
SCC1_RX_BD0_ST=0xB000; //0xB000:当达到MAX_IDL后BUFFER关闭,68302里面没有用
SCC1_RX_BD0_LN=0;
SCC1_RX_BD0_PT=(long)SCC_RBUF[0];
}
void Init_SCC2_Buff()
{
SCC2_TX_BD0_ST=0x2000;
SCC2_TX_BD0_LN=0;
SCC2_TX_BD0_PT=(long)SCC_TBUF[1];
SCC2_RX_BD0_ST=0xB000;
SCC2_RX_BD0_LN=0;
SCC2_RX_BD0_PT=(long)SCC_RBUF[1];
}
void Init_SCC3_Buff()
{
SCC3_TX_BD0_ST=0x2000;
SCC3_TX_BD0_LN=0;
SCC3_TX_BD0_PT=(long)SCC_TBUF[2];
SCC3_RX_BD0_ST=0xB000;
SCC3_RX_BD0_LN=0;
SCC3_RX_BD0_PT=(long)SCC_RBUF[2];
}
void Init_SCC4_Buff()
{
SCC4_TX_BD0_ST=0x2000;
SCC4_TX_BD0_LN=0;
SCC4_TX_BD0_PT=(long)SCC_TBUF[3];
SCC4_RX_BD0_ST=0xB000;
SCC4_RX_BD0_LN=0;
SCC4_RX_BD0_PT=(long)SCC_RBUF[3];
}
void Init_SCC1_Config(void)
{
BRGC1=BRGC_code[SCC_BAUD[0]]; //设置SCC1波特率
RBASE1=SCC1_RX_BD_BASE;
TBASE1=SCC1_TX_BD_BASE;
CR=0x0001; //INIT_TRX_PARAMS|CPM_CR_FLG|CPM_CR_CH_SCC1;
while(CR & CPM_CR_FLG);
RFCR1=0x18; //set Receive FCR to normal
TFCR1=0x18; //set Transmit FCR to normal
MRBLR1=0x00ff; //RX buffer的最大容量
MAX_IDL1=20;
BRKCR1=0x0000; //if a stop transmit command is issued,one break character will be sent
PAREC1=0;
FRMEC1=0;
NOSEC1=0;
BRKEC1=0;
RCCM1=0xC0FF;
UADDR11=0;
UADDR12=0;
TOSEQ1=0;
CHARACTER11=0x8000;
CHARACTER12=0x8000;
CHARACTER13=0x8000;
CHARACTER14=0x8000;
CHARACTER15=0x8000;
CHARACTER16=0x8000;
CHARACTER17=0x8000;
CHARACTER18=0x8000;
SCCE1=0xFFFF;
SCCM1=0x0000;
GSMR_H1=0x00000020;
GSMR_L1=0x00028004; //UART,16X RX\TX clock
//PSMR1=0x3040; //后四位:0,odd parity;5,0 parity;a,even parity;f,1 parity.
//第5位:0:no parity;1:parity enable
//第14位:0,one stop bit;1:two stop bits.
//默认为:8 data bits,one stop bit,no parity.
//PSMR1=0x305A; //even,one stop,8 data bits
//PSMR1=0x3050; //odd,one stop,8 data bits
//PSMR1=0x7040; //no parity 2 stop,8 data bits
switch(SCC_PARITY[0]) //0:no parity,1 stop; 1:even 1 stop; 2:odd 1 stop;
{
case 0:
PSMR1=0x3040;
break;
case 1:
PSMR1=0x305A;
break;
case 2:
PSMR1=0x3050;
break;
default:
PSMR1=0x3040;
break;
}
CR=RESTART_TX|CPM_CR_CH_SCC1|CPM_CR_FLG;
while(CR & CPM_CR_FLG);
}
void Init_SCC2_Config(void)
{
BRGC2=BRGC_code[SCC_BAUD[1]]; //设置SCC2波特率
RBASE2=SCC2_RX_BD_BASE;
TBASE2=SCC2_TX_BD_BASE;
CR=0x0041; //INIT_TRX_PARAMS|CPM_CR_FLG|CPM_CR_CH_SCC1;
while(CR & CPM_CR_FLG);
RFCR2=0x18; //set Receive FCR to normal
TFCR2=0x18; //set Transmit FCR to normal
MRBLR2=0x00FF; //set max no of bytes to 8
MAX_IDL2=20;
BRKCR2=0x0000; //if a stop transmit command is issued,one break character will be sent
PAREC2=0;
FRMEC2=0;
NOSEC2=0;
BRKEC2=0;
RCCM2=0xC0FF;
UADDR21=0;
UADDR22=0;
TOSEQ2=0;
CHARACTER21=0x8000;
CHARACTER22=0x8000;
CHARACTER23=0x8000;
CHARACTER24=0x8000;
CHARACTER25=0x8000;
CHARACTER26=0x8000;
CHARACTER27=0x8000;
CHARACTER28=0x8000;
SCCE2=0xFFFF;
SCCM2=0x0000;
GSMR_H2=0x00000020;
GSMR_L2=0x00028004; //UART,16X RX\TX clock
switch(SCC_PARITY[1]) //0:no parity,1 stop; 1:even 1 stop; 2:odd 1 stop;
{
case 0:
PSMR2=0x3040;
break;
case 1:
PSMR2=0x305A;
break;
case 2:
PSMR2=0x3050;
break;
default:
PSMR2=0x3040;
break;
}
CR=RESTART_TX|CPM_CR_CH_SCC2|CPM_CR_FLG;
while(CR & CPM_CR_FLG);
}
void Init_SCC3_Config(void)
{
BRGC3=BRGC_code[SCC_BAUD[2]]; //设置SCC3波特率
RBASE3=SCC3_RX_BD_BASE;
TBASE3=SCC3_TX_BD_BASE;
CR=0x0081; //INIT_TRX_PARAMS|CPM_CR_FLG|CPM_CR_CH_SCC1;
while(CR & CPM_CR_FLG);
RFCR3=0x18; //set Receive FCR to normal
TFCR3=0x18; //set Transmit FCR to normal
MRBLR3=0x00FF; //set max no of bytes to 8
MAX_IDL3=20;
BRKCR3=0x0000; //if a stop transmit command is issued,one break character will be sent
PAREC3=0;
FRMEC3=0;
NOSEC3=0;
BRKEC3=0;
RCCM3=0xC0FF;
UADDR31=0;
UADDR32=0;
TOSEQ3=0;
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