📄 at91sam9m10.h
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#define AT91C_SFR_DDRDELAY_CLK_3 (0x3) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_4 (0x4) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_5 (0x5) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_6 (0x6) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_7 (0x7) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_8 (0x8) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_9 (0x9) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_10 (0xA) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_11 (0xB) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_12 (0xC) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_13 (0xD) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_14 (0xE) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_15 (0xF) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_16 (0x10) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0 (0xFF << 8) // (SFR) Control DQS0 clock delay
#define AT91C_SFR_DDRDELAY_DQS0_0 (0x0 << 8) // (SFR) minimum delay
#define AT91C_SFR_DDRDELAY_DQS0_1 (0x1 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_2 (0x2 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_3 (0x3 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_4 (0x4 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_5 (0x5 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_6 (0x6 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_7 (0x7 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_8 (0x8 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_9 (0x9 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_10 (0xA << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_11 (0xB << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_12 (0xC << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_13 (0xD << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_14 (0xE << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_15 (0xF << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS0_16 (0x10 << 8) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1 (0xFF << 16) // (SFR) Control DQS1 clock delay
#define AT91C_SFR_DDRDELAY_DQS1_0 (0x0 << 16) // (SFR) minimum delay
#define AT91C_SFR_DDRDELAY_DQS1_1 (0x1 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_2 (0x2 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_3 (0x3 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_4 (0x4 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_5 (0x5 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_6 (0x6 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_7 (0x7 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_8 (0x8 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_9 (0x9 << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_10 (0xA << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_11 (0xB << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_12 (0xC << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_13 (0xD << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_14 (0xE << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_15 (0xF << 16) // (SFR)
#define AT91C_SFR_DDRDELAY_DQS1_16 (0x10 << 16) // (SFR)
// -------- SFR_EBIDELAY : (SFR Offset: 0xc) EBI DDR controller clock delay --------
#define AT91C_SFR_EBIDELAY_CLK (0xFF << 0) // (SFR) Control CLK clock delay
#define AT91C_SFR_EBIDELAY_CLK_0 (0x0) // (SFR) minimum delay
#define AT91C_SFR_EBIDELAY_CLK_1 (0x1) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_2 (0x2) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_3 (0x3) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_4 (0x4) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_5 (0x5) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_6 (0x6) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_7 (0x7) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_8 (0x8) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_9 (0x9) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_10 (0xA) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_11 (0xB) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_12 (0xC) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_13 (0xD) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_14 (0xE) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_15 (0xF) // (SFR)
#define AT91C_SFR_EBIDELAY_CLK_16 (0x10) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0 (0xFF << 8) // (SFR) Control DQS0 clock delay
#define AT91C_SFR_EBIDELAY_DQS0_0 (0x0 << 8) // (SFR) minimum delay
#define AT91C_SFR_EBIDELAY_DQS0_1 (0x1 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_2 (0x2 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_3 (0x3 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_4 (0x4 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_5 (0x5 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_6 (0x6 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_7 (0x7 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_8 (0x8 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_9 (0x9 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_10 (0xA << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_11 (0xB << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_12 (0xC << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_13 (0xD << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_14 (0xE << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_15 (0xF << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS0_16 (0x10 << 8) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1 (0xFF << 16) // (SFR) Control DQS1 clock delay
#define AT91C_SFR_EBIDELAY_DQS1_0 (0x0 << 16) // (SFR) minimum delay
#define AT91C_SFR_EBIDELAY_DQS1_1 (0x1 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_2 (0x2 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_3 (0x3 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_4 (0x4 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_5 (0x5 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_6 (0x6 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_7 (0x7 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_8 (0x8 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_9 (0x9 << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_10 (0xA << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_11 (0xB << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_12 (0xC << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_13 (0xD << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_14 (0xE << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_15 (0xF << 16) // (SFR)
#define AT91C_SFR_EBIDELAY_DQS1_16 (0x10 << 16) // (SFR)
// -------- SFR_UTMICFG : (SFR Offset: 0x10) UTMI Software Reset --------
#define AT91C_SFR_UTMICFG_PORT0 (0x1 << 0) // (SFR) UTMI Software Reset port 0
#define AT91C_SFR_UTMICFG_PORT1 (0x1 << 1) // (SFR) UTMI Software Reset port 1
#define AT91C_SFR_UTMICFG_OHCI_SUSP_INT_ENABLE (0x1 << 2) // (SFR) OHCI Suspend Interrupt enable
// -------- SFR_OHCI_SUSP_INT : (SFR Offset: 0x14) OHCI suspend Interrupt status --------
#define AT91C_SFR_OHCI_SUSP_INT_STATUS (0x3 << 0) // (SFR) OHCI suspend Interrupt status
#define AT91C_SFR_OHCI_SUSP_INT_STATUS_PORT0 (0x1) // (SFR) OHCI suspend Interrupt status for port 0
#define AT91C_SFR_OHCI_SUSP_INT_STATUS_PORT1 (0x2) // (SFR) OHCI suspend Interrupt status for port 1
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG Reserved0[3904]; //
AT91_REG SYS_RSTC_RCR; // Reset Control Register
AT91_REG SYS_RSTC_RSR; // Reset Status Register
AT91_REG SYS_RSTC_RMR; // Reset Mode Register
AT91_REG Reserved1[1]; //
AT91_REG SYS_SHDWC_SHCR; // Shut Down Control Register
AT91_REG SYS_SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SYS_SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved2[1]; //
AT91_REG SYS_RTTC0_RTMR; // Real-time Mode Register
AT91_REG SYS_RTTC0_RTAR; // Real-time Alarm Register
AT91_REG SYS_RTTC0_RTVR; // Real-time Value Register
AT91_REG SYS_RTTC0_RTSR; // Real-time Status Register
AT91_REG SYS_PITC_PIMR; // Period Interval Mode Register
AT91_REG SYS_PITC_PISR; // Period Interval Status Register
AT91_REG SYS_PITC_PIVR; // Period Interval Value Register
AT91_REG SYS_PITC_PIIR; // Period Interval Image Register
AT91_REG SYS_WDTC_WDCR; // Watchdog Control Register
AT91_REG SYS_WDTC_WDMR; // Watchdog Mode Register
AT91_REG SYS_WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved3[1]; //
AT91_REG SYS_SLCKSEL; // Slow Clock Selection Register
AT91_REG Reserved4[3]; //
AT91_REG SYS_GPBR[4]; // General Purpose Register
AT91_REG Reserved5[16]; //
AT91_REG RTC_CR; // Control Register
AT91_REG RTC_MR; // Mode Register
AT91_REG RTC_TIMR; // Time Register
AT91_REG RTC_CALR; // Calendar Register
AT91_REG RTC_TIMALR; // Time Alarm Register
AT91_REG RTC_CALALR; // Calendar Alarm Register
AT91_REG RTC_SR; // Status Register
AT91_REG RTC_SCCR; // Status Clear Command Register
AT91_REG RTC_IER; // Interrupt Enable Register
AT91_REG RTC_IDR; // Interrupt Disable Register
AT91_REG RTC_IMR; // Interrupt Mask Register
AT91_REG RTC_VER; // Valid Entry Register
} AT91S_SYS, *AT91PS_SYS;
#else
#define SLCKSEL (AT91_CAST(AT91_REG *) 0x00003D50) // (SLCKSEL) Slow Clock Selection Register
#define GPBR (AT91_CAST(AT91_REG *) 0x00003D60) // (GPBR) General Purpose Register
#endif
// -------- SLCKSEL : (SYS Offset: 0x3d50) Slow Clock Selection Register --------
#define AT91C_SLCKSEL_RCEN (0x1 << 0) // (SYS) Enable Internal RC Oscillator
#define AT91C_SLCKSEL_OSC32EN (0x1 << 1) // (SYS) Enable External Oscillator
#define AT91C_SLCKSEL_OSC32BYP (0x1 << 2) // (SYS) Bypass External Oscillator
#define AT91C_SLCKSEL_OSCSEL (0x1 << 3) // (SYS) OSC Selection
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