📄 at91sam9m10.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9M10.h
// Object : AT91SAM9M10 definitions
// Generated : AT91 SW Application Group 09/10/2008 (16:04:26)
//
// CVS Reference : /AT91SAM9M10.pl/1.1/Mon Sep 1 13:32:53 2008//
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// CVS Reference : /AES_6149B.pl/1.1/Fri Oct 14 13:30:02 2005//
// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005//
// CVS Reference : /SHA_6156B.pl/1.1/Fri Jun 22 13:26:18 2007//
// CVS Reference : /TRNG_xxxxx.pl/1.1/Wed Jul 18 12:02:58 2007//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9M10_H
#define AT91SAM9M10_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SPECIAL FUNCTION REGISTER
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SFR {
AT91_REG SFR_EMA; // memory Extra Margin Adjustment control
AT91_REG SFR_DDRCFG; // DDR2 SSTL18 control
AT91_REG SFR_DDRDELAY; // DDR2 controller clock delay
AT91_REG SFR_EBIDELAY; // EBI DDR controller clock delay
AT91_REG SFR_UTMICFG; // UTMI Software Reset, and OHCI suspend interrupt control
AT91_REG SFR_INT; // OHCI suspend Interrupt status
} AT91S_SFR, *AT91PS_SFR;
#else
#define SFR_EMA (AT91_CAST(AT91_REG *) 0x00000000) // (SFR_EMA) memory Extra Margin Adjustment control
#define SFR_DDRCFG (AT91_CAST(AT91_REG *) 0x00000004) // (SFR_DDRCFG) DDR2 SSTL18 control
#define SFR_DDRDELAY (AT91_CAST(AT91_REG *) 0x00000008) // (SFR_DDRDELAY) DDR2 controller clock delay
#define SFR_EBIDELAY (AT91_CAST(AT91_REG *) 0x0000000C) // (SFR_EBIDELAY) EBI DDR controller clock delay
#define SFR_UTMICFG (AT91_CAST(AT91_REG *) 0x00000010) // (SFR_UTMICFG) UTMI Software Reset, and OHCI suspend interrupt control
#define SFR_OHCI_SUSP_INT (AT91_CAST(AT91_REG *) 0x00000014) // (SFR_OHCI_SUSP_INT) OHCI suspend Interrupt status
#endif
// -------- SFR_EMA : (SFR Offset: 0x0) memory Extra Margin Adjustment control register --------
#define AT91C_SFR_RAM_EMA (0x7 << 0) // (SFR) SRAM EMA
#define AT91C_SFR_RAM_EMA_0 (0x0) // (SFR) Normal Mode
#define AT91C_SFR_RAM_EMA_1 (0x1) // (SFR) DEBUG MODE 1
#define AT91C_SFR_RAM_EMA_2 (0x2) // (SFR) DEBUG MODE 2
#define AT91C_SFR_RAM_EMA_3 (0x3) // (SFR) DEBUG MODE 3
#define AT91C_SFR_RAM_EMA_4 (0x4) // (SFR) DEBUG MODE 4
#define AT91C_SFR_RAM_EMA_5 (0x5) // (SFR) DEBUG MODE 5
#define AT91C_SFR_RAM_EMA_6 (0x6) // (SFR) DEBUG MODE 6
#define AT91C_SFR_RAM_EMA_7 (0x7) // (SFR) DEBUG MODE 7
#define AT91C_SFR_DPRAM_EMA (0x7 << 4) // (SFR) SRAM EMA
#define AT91C_SFR_DPRAM_EMA_0 (0x0 << 4) // (SFR) Normal Mode
#define AT91C_SFR_DPRAM_EMA_1 (0x1 << 4) // (SFR) DEBUG MODE 1
#define AT91C_SFR_DPRAM_EMA_2 (0x2 << 4) // (SFR) DEBUG MODE 2
#define AT91C_SFR_DPRAM_EMA_3 (0x3 << 4) // (SFR) DEBUG MODE 3
#define AT91C_SFR_DPRAM_EMA_4 (0x4 << 4) // (SFR) DEBUG MODE 4
#define AT91C_SFR_DPRAM_EMA_5 (0x5 << 4) // (SFR) DEBUG MODE 5
#define AT91C_SFR_DPRAM_EMA_6 (0x6 << 4) // (SFR) DEBUG MODE 6
#define AT91C_SFR_DPRAM_EMA_7 (0x7 << 4) // (SFR) DEBUG MODE 7
#define AT91C_SFR_RF_EMA (0x7 << 8) // (SFR) SRAM EMA
#define AT91C_SFR_RF_EMA_0 (0x0 << 8) // (SFR) Normal Mode
#define AT91C_SFR_RF_EMA_1 (0x1 << 8) // (SFR) DEBUG MODE 1
#define AT91C_SFR_RF_EMA_2 (0x2 << 8) // (SFR) DEBUG MODE 2
#define AT91C_SFR_RF_EMA_3 (0x3 << 8) // (SFR) DEBUG MODE 3
#define AT91C_SFR_RF_EMA_4 (0x4 << 8) // (SFR) DEBUG MODE 4
#define AT91C_SFR_RF_EMA_5 (0x5 << 8) // (SFR) DEBUG MODE 5
#define AT91C_SFR_RF_EMA_6 (0x6 << 8) // (SFR) DEBUG MODE 6
#define AT91C_SFR_RF_EMA_7 (0x7 << 8) // (SFR) DEBUG MODE 7
#define AT91C_SFR_DPRF_EMA (0x7 << 12) // (SFR) SRAM EMA
#define AT91C_SFR_DPRF_EMA_0 (0x0 << 12) // (SFR) Normal Mode
#define AT91C_SFR_DPRF_EMA_1 (0x1 << 12) // (SFR) DEBUG MODE 1
#define AT91C_SFR_DPRF_EMA_2 (0x2 << 12) // (SFR) DEBUG MODE 2
#define AT91C_SFR_DPRF_EMA_3 (0x3 << 12) // (SFR) DEBUG MODE 3
#define AT91C_SFR_DPRF_EMA_4 (0x4 << 12) // (SFR) DEBUG MODE 4
#define AT91C_SFR_DPRF_EMA_5 (0x5 << 12) // (SFR) DEBUG MODE 5
#define AT91C_SFR_DPRF_EMA_6 (0x6 << 12) // (SFR) DEBUG MODE 6
#define AT91C_SFR_DPRF_EMA_7 (0x7 << 12) // (SFR) DEBUG MODE 7
#define AT91C_SFR_ROM_EMA (0x7 << 16) // (SFR) SRAM EMA
#define AT91C_SFR_ROM_EMA_0 (0x0 << 16) // (SFR) Normal Mode
#define AT91C_SFR_ROM_EMA_1 (0x1 << 16) // (SFR) DEBUG MODE 1
#define AT91C_SFR_ROM_EMA_2 (0x2 << 16) // (SFR) DEBUG MODE 2
#define AT91C_SFR_ROM_EMA_3 (0x3 << 16) // (SFR) DEBUG MODE 3
#define AT91C_SFR_ROM_EMA_4 (0x4 << 16) // (SFR) DEBUG MODE 4
#define AT91C_SFR_ROM_EMA_5 (0x5 << 16) // (SFR) DEBUG MODE 5
#define AT91C_SFR_ROM_EMA_6 (0x6 << 16) // (SFR) DEBUG MODE 6
#define AT91C_SFR_ROM_EMA_7 (0x7 << 16) // (SFR) DEBUG MODE 7
// -------- SFR_DDRCFG : (SFR Offset: 0x4) DDR2 SSTL18 control register --------
#define AT91C_SFR_DDRCFG_SSTL (0x1 << 0) // (SFR) Control DDR2 pads SSTL mode control
#define AT91C_SFR_DDRCFG_SSTL_NORMAL (0x0) // (SFR) Force pads in SSTL18 mode when DDR2 is connected
#define AT91C_SFR_DDRCFG_SSTL_COMPATIBLE (0x1) // (SFR) LVCMOS level (compatible SSTL18)
#define AT91C_SFR_DDRCFG_CLKDELAY (0x1 << 8) // (SFR) Control DDR2 pads clocks delay on clk, dqs0, dqs1
#define AT91C_SFR_DDRCFG_CLKDELAY_HARD (0x0 << 8) // (SFR) Fixed by hardware
#define AT91C_SFR_DDRCFG_CLKDELAY_SOFT (0x1 << 8) // (SFR) Software must write correct delay value
// -------- SFR_DDRDELAY : (SFR Offset: 0x8) DDR2 controller clock delay --------
#define AT91C_SFR_DDRDELAY_CLK (0xFF << 0) // (SFR) Control CLK clock delay
#define AT91C_SFR_DDRDELAY_CLK_0 (0x0) // (SFR) minimum delay
#define AT91C_SFR_DDRDELAY_CLK_1 (0x1) // (SFR)
#define AT91C_SFR_DDRDELAY_CLK_2 (0x2) // (SFR)
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