📄 at91cap9.h
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#define AT91C_BCRAMC_TCW_4 (0x4) // (BCRAMC) Value : 4
#define AT91C_BCRAMC_TCW_5 (0x5) // (BCRAMC) Value : 5
#define AT91C_BCRAMC_TCW_6 (0x6) // (BCRAMC) Value : 6
#define AT91C_BCRAMC_TCW_7 (0x7) // (BCRAMC) Value : 7
#define AT91C_BCRAMC_TCW_8 (0x8) // (BCRAMC) Value : 8
#define AT91C_BCRAMC_TCW_9 (0x9) // (BCRAMC) Value : 9
#define AT91C_BCRAMC_TCW_10 (0xA) // (BCRAMC) Value : 10
#define AT91C_BCRAMC_TCW_11 (0xB) // (BCRAMC) Value : 11
#define AT91C_BCRAMC_TCW_12 (0xC) // (BCRAMC) Value : 12
#define AT91C_BCRAMC_TCW_13 (0xD) // (BCRAMC) Value : 13
#define AT91C_BCRAMC_TCW_14 (0xE) // (BCRAMC) Value : 14
#define AT91C_BCRAMC_TCW_15 (0xF) // (BCRAMC) Value : 15
#define AT91C_BCRAMC_TCRES (0x3 << 4) // (BCRAMC) CRE Setup
#define AT91C_BCRAMC_TCRES_0 (0x0 << 4) // (BCRAMC) Value : 0
#define AT91C_BCRAMC_TCRES_1 (0x1 << 4) // (BCRAMC) Value : 1
#define AT91C_BCRAMC_TCRES_2 (0x2 << 4) // (BCRAMC) Value : 2
#define AT91C_BCRAMC_TCRES_3 (0x3 << 4) // (BCRAMC) Value : 3
#define AT91C_BCRAMC_TCKA (0xF << 8) // (BCRAMC) WE High to CLK Valid
#define AT91C_BCRAMC_TCKA_0 (0x0 << 8) // (BCRAMC) Value : 0
#define AT91C_BCRAMC_TCKA_1 (0x1 << 8) // (BCRAMC) Value : 1
#define AT91C_BCRAMC_TCKA_2 (0x2 << 8) // (BCRAMC) Value : 2
#define AT91C_BCRAMC_TCKA_3 (0x3 << 8) // (BCRAMC) Value : 3
#define AT91C_BCRAMC_TCKA_4 (0x4 << 8) // (BCRAMC) Value : 4
#define AT91C_BCRAMC_TCKA_5 (0x5 << 8) // (BCRAMC) Value : 5
#define AT91C_BCRAMC_TCKA_6 (0x6 << 8) // (BCRAMC) Value : 6
#define AT91C_BCRAMC_TCKA_7 (0x7 << 8) // (BCRAMC) Value : 7
#define AT91C_BCRAMC_TCKA_8 (0x8 << 8) // (BCRAMC) Value : 8
#define AT91C_BCRAMC_TCKA_9 (0x9 << 8) // (BCRAMC) Value : 9
#define AT91C_BCRAMC_TCKA_10 (0xA << 8) // (BCRAMC) Value : 10
#define AT91C_BCRAMC_TCKA_11 (0xB << 8) // (BCRAMC) Value : 11
#define AT91C_BCRAMC_TCKA_12 (0xC << 8) // (BCRAMC) Value : 12
#define AT91C_BCRAMC_TCKA_13 (0xD << 8) // (BCRAMC) Value : 13
#define AT91C_BCRAMC_TCKA_14 (0xE << 8) // (BCRAMC) Value : 14
#define AT91C_BCRAMC_TCKA_15 (0xF << 8) // (BCRAMC) Value : 15
// -------- BCRAMC_HSR : (BCRAMC Offset: 0x8) BCRAM Controller High Speed Register --------
#define AT91C_BCRAMC_DA (0x1 << 0) // (BCRAMC) Decode Cycle Enable Bit
#define AT91C_BCRAMC_DA_DISABLE (0x0) // (BCRAMC) Disable Decode Cycle
#define AT91C_BCRAMC_DA_ENABLE (0x1) // (BCRAMC) Enable Decode Cycle
// -------- BCRAMC_LPR : (BCRAMC Offset: 0xc) BCRAM Controller Low-power Register --------
#define AT91C_BCRAMC_PAR (0x7 << 0) // (BCRAMC) Partial Array Refresh
#define AT91C_BCRAMC_PAR_FULL (0x0) // (BCRAMC) Full Refresh
#define AT91C_BCRAMC_PAR_PARTIAL_BOTTOM_HALF (0x1) // (BCRAMC) Partial Bottom Half Refresh
#define AT91C_BCRAMC_PAR_PARTIAL_BOTTOM_QUARTER (0x2) // (BCRAMC) Partial Bottom Quarter Refresh
#define AT91C_BCRAMC_PAR_PARTIAL_BOTTOM_EIGTH (0x3) // (BCRAMC) Partial Bottom eigth Refresh
#define AT91C_BCRAMC_PAR_NONE (0x4) // (BCRAMC) Not Refreshed
#define AT91C_BCRAMC_PAR_PARTIAL_TOP_HALF (0x5) // (BCRAMC) Partial Top Half Refresh
#define AT91C_BCRAMC_PAR_PARTIAL_TOP_QUARTER (0x6) // (BCRAMC) Partial Top Quarter Refresh
#define AT91C_BCRAMC_PAR_PARTIAL_TOP_EIGTH (0x7) // (BCRAMC) Partial Top eigth Refresh
#define AT91C_BCRAMC_TCR (0x3 << 4) // (BCRAMC) Temperature Compensated Self Refresh
#define AT91C_BCRAMC_TCR_85C (0x0 << 4) // (BCRAMC) +85C Temperature
#define AT91C_BCRAMC_TCR_INTERNAL_OR_70C (0x1 << 4) // (BCRAMC) Internal Sensor or +70C Temperature
#define AT91C_BCRAMC_TCR_45C (0x2 << 4) // (BCRAMC) +45C Temperature
#define AT91C_BCRAMC_TCR_15C (0x3 << 4) // (BCRAMC) +15C Temperature
#define AT91C_BCRAMC_LPCB (0x3 << 8) // (BCRAMC) Low-power Command Bit
#define AT91C_BCRAMC_LPCB_DISABLE (0x0 << 8) // (BCRAMC) Disable Low Power Features
#define AT91C_BCRAMC_LPCB_STANDBY (0x1 << 8) // (BCRAMC) Enable Cellular RAM Standby Mode
#define AT91C_BCRAMC_LPCB_DEEP_POWER_DOWN (0x2 << 8) // (BCRAMC) Enable Cellular RAM Deep Power Down Mode
// -------- BCRAMC_MDR : (BCRAMC Offset: 0x10) BCRAM Controller Memory Device Register --------
#define AT91C_BCRAMC_MD (0x3 << 0) // (BCRAMC) Memory Device Type
#define AT91C_BCRAMC_MD_BCRAM_V10 (0x0) // (BCRAMC) Busrt Cellular RAM v1.0
#define AT91C_BCRAMC_MD_BCRAM_V15 (0x1) // (BCRAMC) Busrt Cellular RAM v1.5
#define AT91C_BCRAMC_MD_BCRAM_V20 (0x2) // (BCRAMC) Busrt Cellular RAM v2.0
// *****************************************************************************
// SOFTWARE API DEFINITION FOR DDR/SDRAM Controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SDDRC {
AT91_REG SDDRC_MR; //
AT91_REG SDDRC_RTR; //
AT91_REG SDDRC_CR; //
AT91_REG SDDRC_T0PR; //
AT91_REG SDDRC_T1PR; //
AT91_REG SDDRC_HS; //
AT91_REG SDDRC_LPR; //
AT91_REG SDDRC_MDR; //
AT91_REG Reserved0[55]; //
AT91_REG SDDRC_VERSION; //
} AT91S_SDDRC, *AT91PS_SDDRC;
#else
#define SDDRC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDDRC_MR)
#define SDDRC_RTR (AT91_CAST(AT91_REG *) 0x00000004) // (SDDRC_RTR)
#define SDDRC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDDRC_CR)
#define SDDRC_T0PR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDDRC_T0PR)
#define SDDRC_T1PR (AT91_CAST(AT91_REG *) 0x00000010) // (SDDRC_T1PR)
#define SDDRC_HS (AT91_CAST(AT91_REG *) 0x00000014) // (SDDRC_HS)
#define SDDRC_LPR (AT91_CAST(AT91_REG *) 0x00000018) // (SDDRC_LPR)
#define SDDRC_MDR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDDRC_MDR)
#define SDDRC_VERSION (AT91_CAST(AT91_REG *) 0x000000FC) // (SDDRC_VERSION)
#endif
// -------- SDDRC_MR : (SDDRC Offset: 0x0) --------
#define AT91C_MODE (0xF << 0) // (SDDRC)
#define AT91C_MODE_NORMAL_CMD (0x0) // (SDDRC) Normal Mode
#define AT91C_MODE_NOP_CMD (0x1) // (SDDRC) Issue a NOP Command at every access
#define AT91C_MODE_PRCGALL_CMD (0x2) // (SDDRC) Issue a All Banks Precharge Command at every access
#define AT91C_MODE_LMR_CMD (0x3) // (SDDRC) Issue a Load Mode Register at every access
#define AT91C_MODE_RFSH_CMD (0x4) // (SDDRC) Issue a Refresh
#define AT91C_MODE_EXT_LMR_CMD (0x5) // (SDDRC) Issue an Extended Load Mode Register
#define AT91C_MODE_DEEP_CMD (0x6) // (SDDRC) Enter Deep Power Mode
// -------- SDDRC_RTR : (SDDRC Offset: 0x4) --------
#define AT91C_COUNT (0xFFF << 0) // (SDDRC)
// -------- SDDRC_CR : (SDDRC Offset: 0x8) --------
#define AT91C_NC (0x3 << 0) // (SDDRC)
#define AT91C_NC_DDR9_SDR8 (0x0) // (SDDRC) DDR 9 Bits | SDR 8 Bits
#define AT91C_NC_DDR10_SDR9 (0x1) // (SDDRC) DDR 10 Bits | SDR 9 Bits
#define AT91C_NC_DDR11_SDR10 (0x2) // (SDDRC) DDR 11 Bits | SDR 10 Bits
#define AT91C_NC_DDR12_SDR11 (0x3) // (SDDRC) DDR 12 Bits | SDR 11 Bits
#define AT91C_NR (0x3 << 2) // (SDDRC)
#define AT91C_NR_11 (0x0 << 2) // (SDDRC) 11 Bits
#define AT91C_NR_12 (0x1 << 2) // (SDDRC) 12 Bits
#define AT91C_NR_13 (0x2 << 2) // (SDDRC) 13 Bits
#define AT91C_NR_14 (0x3 << 2) // (SDDRC) 14 Bits
#define AT91C_CAS (0x7 << 4) // (SDDRC)
#define AT91C_CAS_2 (0x2 << 4) // (SDDRC) 2 cycles
#define AT91C_CAS_3 (0x3 << 4) // (SDDRC) 3 cycles
#define AT91C_DLL (0x1 << 7) // (SDDRC)
#define AT91C_DLL_RESET_DISABLED (0x0 << 7) // (SDDRC) Disable DLL reset
#define AT91C_DLL_RESET_ENABLED (0x1 << 7) // (SDDRC) Enable DLL reset
#define AT91C_DIC_DS (0x1 << 8) // (SDDRC)
// -------- SDDRC_T0PR : (SDDRC Offset: 0xc) --------
#define AT91C_TRAS (0xF << 0) // (SDDRC)
#define AT91C_TRAS_0 (0x0) // (SDDRC) Value : 0
#define AT91C_TRAS_1 (0x1) // (SDDRC) Value : 1
#define AT91C_TRAS_2 (0x2) // (SDDRC) Value : 2
#define AT91C_TRAS_3 (0x3) // (SDDRC) Value : 3
#define AT91C_TRAS_4 (0x4) // (SDDRC) Value : 4
#define AT91C_TRAS_5 (0x5) // (SDDRC) Value : 5
#define AT91C_TRAS_6 (0x6) // (SDDRC) Value : 6
#define AT91C_TRAS_7 (0x7) // (SDDRC) Value : 7
#define AT91C_TRAS_8 (0x8) // (SDDRC) Value : 8
#define AT91C_TRAS_9 (0x9) // (SDDRC) Value : 9
#define AT91C_TRAS_10 (0xA) // (SDDRC) Value : 10
#define AT91C_TRAS_11 (0xB) // (SDDRC) Value : 11
#define AT91C_TRAS_12 (0xC) // (SDDRC) Value : 12
#define AT91C_TRAS_13 (0xD) // (SDDRC) Value : 13
#define AT91C_TRAS_14 (0xE) // (SDDRC) Value : 14
#define AT91C_TRAS_15 (0xF) // (SDDRC) Value : 15
#define AT91C_TRCD (0xF << 4) // (SDDRC)
#define AT91C_TRCD_0 (0x0 << 4) // (SDDRC) Value : 0
#define AT91C_TRCD_1 (0x1 << 4) // (SDDRC) Value : 1
#define AT91C_TRCD_2 (0x2 << 4) // (SDDRC) Value : 2
#define AT91C_TRCD_3 (0x3 << 4) // (SDDRC) Value : 3
#define AT91C_TRCD_4 (0x4 << 4) // (SDDRC) Value : 4
#define AT91C_TRCD_5 (0x5 << 4) // (SDDRC) Value : 5
#define AT91C_TRCD_6 (0x6 << 4) // (SDDRC) Value : 6
#define AT91C_TRCD_7 (0x7 << 4) // (SDDRC) Value : 7
#define AT91C_TRCD_8 (0x8 << 4) // (SDDRC) Value : 8
#define AT91C_TRCD_9 (0x9 << 4) // (SDDRC) Value : 9
#define AT91C_TRCD_10 (0xA << 4) // (SDDRC) Value : 10
#define AT91C_TRCD_11 (0xB << 4) // (SDDRC) Value : 11
#define AT91C_TRCD_12 (0xC << 4) // (SDDRC) Value : 12
#define AT91C_TRCD_13 (0xD << 4) // (SDDRC) Value : 13
#define AT91C_TRCD_14 (0xE << 4) // (SDDRC) Value : 14
#define AT91C_TRCD_15 (0xF << 4) // (SDDRC) Value : 15
#define AT91C_TWR (0xF << 8) // (SDDRC)
#define AT91C_TWR_0 (0x0 << 8) // (SDDRC) Value : 0
#define AT91C_TWR_1 (0x1 << 8) // (SDDRC) Value : 1
#define AT91C_TWR_2 (0x2 << 8) // (SDDRC) Value : 2
#define AT91C_TWR_3 (0x3 << 8) // (SDDRC) Value : 3
#define AT91C_TWR_4 (0x4 << 8) // (SDDRC) Value : 4
#define AT91C_TWR_5 (0x5 << 8) // (SDDRC) Value : 5
#define AT91C_TWR_6 (0x6 << 8) // (SDDRC) Value : 6
#define AT91C_TWR_7 (0x7 << 8) // (SDDRC) Value : 7
#define AT91C_TWR_8 (0x8 << 8) // (SDDRC) Value : 8
#define AT91C_TWR_9 (0x9 << 8) // (SDDRC) Value : 9
#define AT91C_TWR_10 (0xA << 8) // (SDDRC) Value : 10
#define AT91C_TWR_11 (0xB << 8) // (SDDRC) Value : 11
#define AT91C_TWR_12 (0xC << 8) // (SDDRC) Value : 12
#define AT91C_TWR_13 (0xD << 8) // (SDDRC) Value : 13
#define AT91C_TWR_14 (0xE << 8) // (SDDRC) Value : 14
#define AT91C_TWR_15 (0xF << 8) // (SDDRC) Value : 15
#define AT91C_TRC (0xF << 12) // (SDDRC)
#define AT91C_TRC_0 (0x0 << 12) // (SDDRC) Value : 0
#define AT91C_TRC_1 (0x1 << 12) // (SDDRC) Value : 1
#define AT91C_TRC_2 (0x2 << 12) // (SDDRC) Value : 2
#define AT91C_TRC_3 (0x3 << 12) // (SDDRC) Value : 3
#define AT91C_TRC_4 (0x4 << 12) // (SDDRC) Value : 4
#define AT91C_TRC_5 (0x5 << 12) // (SDDRC) Value : 5
#define AT91C_TRC_6 (0x6 << 12) // (SDDRC) Value : 6
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