📄 at91cap9.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91CAP9_UMC.h
// Object : AT91CAP9_UMC definitions
// Generated : AT91 SW Application Group 09/12/2008 (11:25:46)
//
// CVS Reference : /AT91CAP9_UMC.pl/1.10/Tue Jun 10 12:28:42 2008//
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// CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005//
// CVS Reference : /HBCRAMC1_XXXX.pl/1.1/Wed Jun 14 07:59:13 2006//
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// ----------------------------------------------------------------------------
#ifndef AT91CAP9_UMC_H
#define AT91CAP9_UMC_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Error Correction Code controller
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_ECC {
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved0[58]; //
AT91_REG ECC_VR; // ECC Version register
} AT91S_ECC, *AT91PS_ECC;
#else
#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register
#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register
#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register
#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register
#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register
#define ECC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (ECC_VR) ECC Version register
#endif
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error
#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error
#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error
#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
#define AT91C_ECC_VR (0xF << 0) // (ECC) ECC version register
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Busr Cellular RAM Controller Interface
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_BCRAMC {
AT91_REG BCRAMC_CR; // BCRAM Controller Configuration Register
AT91_REG BCRAMC_TPR; // BCRAM Controller Timing Parameter Register
AT91_REG BCRAMC_HSR; // BCRAM Controller High Speed Register
AT91_REG BCRAMC_LPR; // BCRAM Controller Low Power Register
AT91_REG BCRAMC_MDR; // BCRAM Memory Device Register
AT91_REG Reserved0[54]; //
AT91_REG BCRAMC_PADDSR; // BCRAM PADDR Size Register
AT91_REG BCRAMC_IPNR1; // BCRAM IP Name Register 1
AT91_REG BCRAMC_IPNR2; // BCRAM IP Name Register 2
AT91_REG BCRAMC_IPFR; // BCRAM IP Features Register
AT91_REG BCRAMC_VR; // BCRAM Version Register
} AT91S_BCRAMC, *AT91PS_BCRAMC;
#else
#define BCRAMC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (BCRAMC_CR) BCRAM Controller Configuration Register
#define BCRAMC_TPR (AT91_CAST(AT91_REG *) 0x00000004) // (BCRAMC_TPR) BCRAM Controller Timing Parameter Register
#define BCRAMC_HSR (AT91_CAST(AT91_REG *) 0x00000008) // (BCRAMC_HSR) BCRAM Controller High Speed Register
#define BCRAMC_LPR (AT91_CAST(AT91_REG *) 0x0000000C) // (BCRAMC_LPR) BCRAM Controller Low Power Register
#define BCRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000010) // (BCRAMC_MDR) BCRAM Memory Device Register
#define BCRAMC_PADDSR (AT91_CAST(AT91_REG *) 0x000000EC) // (BCRAMC_PADDSR) BCRAM PADDR Size Register
#define BCRAMC_IPNR1 (AT91_CAST(AT91_REG *) 0x000000F0) // (BCRAMC_IPNR1) BCRAM IP Name Register 1
#define BCRAMC_IPNR2 (AT91_CAST(AT91_REG *) 0x000000F4) // (BCRAMC_IPNR2) BCRAM IP Name Register 2
#define BCRAMC_IPFR (AT91_CAST(AT91_REG *) 0x000000F8) // (BCRAMC_IPFR) BCRAM IP Features Register
#define BCRAMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (BCRAMC_VR) BCRAM Version Register
#endif
// -------- BCRAMC_CR : (BCRAMC Offset: 0x0) BCRAM Controller Configuration Register --------
#define AT91C_BCRAMC_EN (0x1 << 0) // (BCRAMC) Enable
#define AT91C_BCRAMC_CAS (0x7 << 4) // (BCRAMC) CAS Latency
#define AT91C_BCRAMC_CAS_2 (0x2 << 4) // (BCRAMC) 2 cycles Latency for Cellular RAM v1.0/1.5/2.0
#define AT91C_BCRAMC_CAS_3 (0x3 << 4) // (BCRAMC) 3 cycles Latency for Cellular RAM v1.0/1.5/2.0
#define AT91C_BCRAMC_CAS_4 (0x4 << 4) // (BCRAMC) 4 cycles Latency for Cellular RAM v1.5/2.0
#define AT91C_BCRAMC_CAS_5 (0x5 << 4) // (BCRAMC) 5 cycles Latency for Cellular RAM v1.5/2.0
#define AT91C_BCRAMC_CAS_6 (0x6 << 4) // (BCRAMC) 6 cycles Latency for Cellular RAM v1.5/2.0
#define AT91C_BCRAMC_DBW (0x1 << 8) // (BCRAMC) Data Bus Width
#define AT91C_BCRAMC_DBW_32_BITS (0x0 << 8) // (BCRAMC) 32 Bits datas bus
#define AT91C_BCRAMC_DBW_16_BITS (0x1 << 8) // (BCRAMC) 16 Bits datas bus
#define AT91C_BCRAM_NWIR (0x3 << 12) // (BCRAMC) Number Of Words in Row
#define AT91C_BCRAM_NWIR_64 (0x0 << 12) // (BCRAMC) 64 Words in Row
#define AT91C_BCRAM_NWIR_128 (0x1 << 12) // (BCRAMC) 128 Words in Row
#define AT91C_BCRAM_NWIR_256 (0x2 << 12) // (BCRAMC) 256 Words in Row
#define AT91C_BCRAM_NWIR_512 (0x3 << 12) // (BCRAMC) 512 Words in Row
#define AT91C_BCRAM_ADMX (0x1 << 16) // (BCRAMC) ADDR / DATA Mux
#define AT91C_BCRAM_ADMX_NO_MUX (0x0 << 16) // (BCRAMC) No ADD/DATA Mux for Cellular RAM v1.0/1.5/2.0
#define AT91C_BCRAM_ADMX_MUX (0x1 << 16) // (BCRAMC) ADD/DATA Mux Only for Cellular RAM v2.0
#define AT91C_BCRAM_DS (0x3 << 20) // (BCRAMC) Drive Strength
#define AT91C_BCRAM_DS_FULL_DRIVE (0x0 << 20) // (BCRAMC) Full Cellular RAM Drive
#define AT91C_BCRAM_DS_HALF_DRIVE (0x1 << 20) // (BCRAMC) Half Cellular RAM Drive
#define AT91C_BCRAM_DS_QUARTER_DRIVE (0x2 << 20) // (BCRAMC) Quarter Cellular RAM Drive
#define AT91C_BCRAM_VFLAT (0x1 << 24) // (BCRAMC) Variable or Fixed Latency
#define AT91C_BCRAM_VFLAT_VARIABLE (0x0 << 24) // (BCRAMC) Variable Latency
#define AT91C_BCRAM_VFLAT_FIXED (0x1 << 24) // (BCRAMC) Fixed Latency
// -------- BCRAMC_TPR : (BCRAMC Offset: 0x4) BCRAMC Timing Parameter Register --------
#define AT91C_BCRAMC_TCW (0xF << 0) // (BCRAMC) Chip Enable to End of Write
#define AT91C_BCRAMC_TCW_0 (0x0) // (BCRAMC) Value : 0
#define AT91C_BCRAMC_TCW_1 (0x1) // (BCRAMC) Value : 1
#define AT91C_BCRAMC_TCW_2 (0x2) // (BCRAMC) Value : 2
#define AT91C_BCRAMC_TCW_3 (0x3) // (BCRAMC) Value : 3
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