📄 usbd_udphs.lst
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891
892 bEndpoint = 0;
893 pEndpoint = &(endpoints[bEndpoint]);
894 bType = USBEndpointDescriptor_CONTROL;
895 bEndpointDir = 0;
896 pEndpoint->size = BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0);
897 pEndpoint->bank = BOARD_USB_ENDPOINTS_BANKS(0);
898 }
899 else {
900
901 // The endpoint number
902 bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor);
903 pEndpoint = &(endpoints[bEndpoint]);
904 // Transfer type: Control, Isochronous, Bulk, Interrupt
905 bType = USBEndpointDescriptor_GetType(pDescriptor);
906 // Direction, ignored for control endpoints
907 bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor);
908 pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor);
909 pEndpoint->bank = BOARD_USB_ENDPOINTS_BANKS(bEndpoint);
910 }
911
912 // Abort the current transfer is the endpoint was configured and in
913 // Write or Read state
914 if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING)
915 || (pEndpoint->state == UDP_ENDPOINT_SENDING) ) {
916
917 UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_RESET);
918 }
919 pEndpoint->state = UDP_ENDPOINT_IDLE;
920
921 // Disable endpoint
922 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_SHRT_PCKT
923 | AT91C_UDPHS_BUSY_BANK
924 | AT91C_UDPHS_NAK_OUT
925 | AT91C_UDPHS_NAK_IN
926 | AT91C_UDPHS_STALL_SNT
927 | AT91C_UDPHS_RX_SETUP
928 | AT91C_UDPHS_TX_PK_RDY
929 | AT91C_UDPHS_TX_COMPLT
930 | AT91C_UDPHS_RX_BK_RDY
931 | AT91C_UDPHS_ERR_OVFLW
932 | AT91C_UDPHS_MDATA_RX
933 | AT91C_UDPHS_DATAX_RX
934 | AT91C_UDPHS_NYET_DIS
935 | AT91C_UDPHS_INTDIS_DMA
936 | AT91C_UDPHS_AUTO_VALID
937 | AT91C_UDPHS_EPT_DISABL;
938
939 // Reset Endpoint Fifos
940 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_TOGGLESQ | AT91C_UDPHS_FRCESTALL;
941 AT91C_BASE_UDPHS->UDPHS_EPTRST = 1<<bEndpoint;
942
943 // Configure endpoint
944 if( pEndpoint->size <= 8 ) {
945 bSizeEpt = 0;
946 }
947 else if ( pEndpoint->size <= 16 ) {
948 bSizeEpt = 1;
949 }
950 else if ( pEndpoint->size <= 32 ) {
951 bSizeEpt = 2;
952 }
953 else if ( pEndpoint->size <= 64 ) {
954 bSizeEpt = 3;
955 }
956 else if ( pEndpoint->size <= 128 ) {
957 bSizeEpt = 4;
958 }
959 else if ( pEndpoint->size <= 256 ) {
960 bSizeEpt = 5;
961 }
962 else if ( pEndpoint->size <= 512 ) {
963 bSizeEpt = 6;
964 }
965 else if ( pEndpoint->size <= 1024 ) {
966 bSizeEpt = 7;
967 } //else {
968 // sizeEpt = 0; // control endpoint
969 //}
970
971 // Configure endpoint
972 if (bType == USBEndpointDescriptor_CONTROL) {
973
974 // Enable endpoint IT for control endpoint
975 AT91C_BASE_UDPHS->UDPHS_IEN |= (1<<SHIFT_INTERUPT<<bEndpoint);
976 }
977
978
979 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG = bSizeEpt
980 | (bEndpointDir << 3)
981 | (bType << 4)
982 | ((pEndpoint->bank) << 6);
983
984 while( (signed int)AT91C_UDPHS_EPT_MAPD != (signed int)((AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG) & AT91C_UDPHS_EPT_MAPD) ) {
985
986 // resolved by clearing the reset IT in good place
987 TRACE_ERROR("PB bEndpoint: 0x%X\n\r", bEndpoint);
988 TRACE_ERROR("PB bSizeEpt: 0x%X\n\r", bSizeEpt);
989 TRACE_ERROR("PB bEndpointDir: 0x%X\n\r", bEndpointDir);
990 TRACE_ERROR("PB bType: 0x%X\n\r", bType);
991 TRACE_ERROR("PB pEndpoint->bank: 0x%X\n\r", pEndpoint->bank);
992 TRACE_ERROR("PB UDPHS_EPTCFG: 0x%X\n\r", AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG);
993 for(;;);
994 }
995
996 if (bType == USBEndpointDescriptor_CONTROL) {
997
998 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_RX_BK_RDY
999 | AT91C_UDPHS_RX_SETUP
1000 | AT91C_UDPHS_EPT_ENABL;
1001 }
1002 else {
1003 #ifndef DMA
1004 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_EPT_ENABL;
1005 #else
1006 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_AUTO_VALID
1007 | AT91C_UDPHS_EPT_ENABL;
1008 #endif
1009 }
1010
1011 }
1012
1013 //------------------------------------------------------------------------------
1014 /// Sends data through an USB endpoint (IN)
1015 /// Sets up the transfer descriptor, write one or two data payloads
1016 /// (depending on the number of FIFO banks for the endpoint) and then
1017 /// starts the actual transfer. The operation is complete when all
1018 /// the data has been sent.
1019 /// \param bEndpoint Index of endpoint
1020 /// \param *pData Data to be written
1021 /// \param dLength Data length to be send
1022 /// \param fCallback Callback to be call after the success command
1023 /// \param *pArgument Callback argument
1024 /// \return USBD_STATUS_LOCKED or USBD_STATUS_SUCCESS
1025 //------------------------------------------------------------------------------
1026 char USBD_Write( unsigned char bEndpoint,
1027 const void *pData,
1028 unsigned int dLength,
1029 TransferCallback fCallback,
1030 void *pArgument )
1031 {
1032 Endpoint *pEndpoint = &(endpoints[bEndpoint]);
1033 Transfer *pTransfer = &(pEndpoint->transfer);
1034
1035 // Return if the endpoint is not in IDLE state
1036 if (pEndpoint->state != UDP_ENDPOINT_IDLE) {
1037
1038 return USBD_STATUS_LOCKED;
1039 }
1040
1041 TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength);
1042
1043 // Setup the transfer descriptor
1044 pTransfer->pData = (void *) pData;
1045 pTransfer->remaining = dLength;
1046 pTransfer->buffered = 0;
1047 pTransfer->transferred = 0;
1048 pTransfer->fCallback = fCallback;
1049 pTransfer->pArgument = pArgument;
1050
1051 // Send one packet
1052 pEndpoint->state = UDP_ENDPOINT_SENDING;
1053
1054 #ifdef DMA
1055 // Test if endpoint type control
1056 if(AT91C_UDPHS_EPT_TYPE_CTL_EPT == (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG))) {
1057 #endif
1058 // Enable endpoint IT
1059 AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_INTERUPT << bEndpoint);
1060 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_TX_PK_RDY;
1061
1062 #ifdef DMA
1063 }
1064 else {
1065
1066 if( pTransfer->remaining == 0 ) {
1067 // DMA not handle ZLP
1068 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY;
1069 // Enable endpoint IT
1070 AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_INTERUPT << bEndpoint);
1071 AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_TX_PK_RDY;
1072 }
1073 else {
1074 // Others endpoints (not control)
1075 if( pTransfer->remaining > DMA_MAX_FIFO_SIZE ) {
1076
1077 // Transfer the max
1078 pTransfer->buffered = DMA_MAX_FIFO_SIZE;
1079 }
1080 else {
1081 // Transfer the good size
1082 pTransfer->buffered = pTransfer->remaining;
1083 }
1084
1085 TRACE_DEBUG_WP("\n\r_WR:%d ", pTransfer->remaining );
1086 TRACE_DEBUG_WP("B:%d ", pTransfer->buffered );
1087 TRACE_DEBUG_WP("T:%d ", pTransfer->transferred );
1088
1089 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS = (unsigned int)(pTransfer->pData);
1090
1091 // Clear unwanted interrupts
1092 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS;
1093 // Enable DMA endpoint interrupt
1094 AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint);
1095 // DMA config
1096 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; // raz
1097 AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL =
1098 ( ((pTransfer->buffered << 16) & AT91C_UDPHS_BUFF_COUNT)
1099 | AT91C_UDPHS_END_B_EN
1100 | AT91C_UDPHS_END_BUFFIT
1101 | AT91C_UDPHS_CHANN_ENB );
1102 }
1103 }
1104 #endif
1105
1106 return USBD_STATUS_SUCCESS;
1107 }
1108
1109 //------------------------------------------------------------------------------
1110 /// Reads incoming data on an USB endpoint (OUT)
1111 /// \param bEndpoint Index of endpoint
1112 /// \param *pData Data to be readen
1113 /// \param dLength Data length to be receive
1114 /// \param fCallback Callback to be call after the success command
1115 /// \param *pArgument Callback argument
1116 /// \return USBD_STATUS_LOCKED or USBD_STATUS_SUCCESS
1117 //------------------------------------------------------------------------------
1118 char USBD_Read( unsigned char bEndpoint,
1119 void *pData,
1120 unsigned int dLength,
1121 TransferCallback fCallback,
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