📄 board_lowlevel.lst
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\ 0000000C C00FC0E3 BIC R0,R0,#0x300
\ 00000010 0110A0E3 MOV R1,#+1
\ 00000014 401C81E3 ORR R1,R1,#0x4000
\ 00000018 001080E5 STR R1,[R0, #+0]
121 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
\ ??LowLevelInit_0:
\ 0000001C 9700E0E3 MVN R0,#+151
\ 00000020 C00FC0E3 BIC R0,R0,#0x300
\ 00000024 000090E5 LDR R0,[R0, #+0]
\ 00000028 010010E3 TST R0,#0x1
\ 0000002C FAFFFF0A BEQ ??LowLevelInit_0
122
123 /* Initialize PLL at 96MHz (96.109) and USB clock to 48MHz */
124 AT91C_BASE_PMC->PMC_PLLR = BOARD_USBDIV | BOARD_CKGR_PLL | BOARD_PLLCOUNT
125 | BOARD_MUL | BOARD_DIV;
\ 00000030 D300E0E3 MVN R0,#+211
\ 00000034 C00FC0E3 BIC R0,R0,#0x300
\ 00000038 2C119FE5 LDR R1,??LowLevelInit_1 ;; 0x1048100e
\ 0000003C 001080E5 STR R1,[R0, #+0]
126 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK));
\ ??LowLevelInit_2:
\ 00000040 9700E0E3 MVN R0,#+151
\ 00000044 C00FC0E3 BIC R0,R0,#0x300
\ 00000048 000090E5 LDR R0,[R0, #+0]
\ 0000004C 040010E3 TST R0,#0x4
\ 00000050 FAFFFF0A BEQ ??LowLevelInit_2
127
128 /* Wait for the master clock if it was already initialized */
129 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??LowLevelInit_3:
\ 00000054 9700E0E3 MVN R0,#+151
\ 00000058 C00FC0E3 BIC R0,R0,#0x300
\ 0000005C 000090E5 LDR R0,[R0, #+0]
\ 00000060 080010E3 TST R0,#0x8
\ 00000064 FAFFFF0A BEQ ??LowLevelInit_3
130
131 /* Switch to fast clock
132 **********************/
133 /* Switch to slow clock + prescaler */
134 AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER;
\ 00000068 CF00E0E3 MVN R0,#+207
\ 0000006C C00FC0E3 BIC R0,R0,#0x300
\ 00000070 0410A0E3 MOV R1,#+4
\ 00000074 001080E5 STR R1,[R0, #+0]
135 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??LowLevelInit_4:
\ 00000078 9700E0E3 MVN R0,#+151
\ 0000007C C00FC0E3 BIC R0,R0,#0x300
\ 00000080 000090E5 LDR R0,[R0, #+0]
\ 00000084 080010E3 TST R0,#0x8
\ 00000088 FAFFFF0A BEQ ??LowLevelInit_4
136
137 /* Switch to fast clock + prescaler */
138 AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
\ 0000008C CF00E0E3 MVN R0,#+207
\ 00000090 C00FC0E3 BIC R0,R0,#0x300
\ 00000094 000090E5 LDR R0,[R0, #+0]
\ 00000098 030080E3 ORR R0,R0,#0x3
\ 0000009C CF10E0E3 MVN R1,#+207
\ 000000A0 C01FC1E3 BIC R1,R1,#0x300
\ 000000A4 000081E5 STR R0,[R1, #+0]
139 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??LowLevelInit_5:
\ 000000A8 380081E2 ADD R0,R1,#+56
\ 000000AC 000090E5 LDR R0,[R0, #+0]
\ 000000B0 080010E3 TST R0,#0x8
\ 000000B4 FBFFFF0A BEQ ??LowLevelInit_5
140 //#endif //#if !defined(sdram)
141
142 /* Initialize AIC
143 ****************/
144 AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
\ 000000B8 DB00E0E3 MVN R0,#+219
\ 000000BC E00EC0E3 BIC R0,R0,#0xE00
\ 000000C0 0010E0E3 MVN R1,#+0
\ 000000C4 A41000E4 STR R1,[R0], #-164
145 AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler;
\ 000000C8 A0109FE5 LDR R1,??LowLevelInit_1+0x4 ;; defaultFiqHandler
\ 000000CC 001080E5 STR R1,[R0, #+0]
146 for (i = 1; i < 31; i++) {
\ 000000D0 040080E3 ORR R0,R0,#0x4
\ 000000D4 1E10A0E3 MOV R1,#+30
\ 000000D8 94209FE5 LDR R2,??LowLevelInit_1+0x8 ;; defaultIrqHandler
147
148 AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler;
\ ??LowLevelInit_6:
\ 000000DC 042080E4 STR R2,[R0], #+4
149 }
\ 000000E0 011051E2 SUBS R1,R1,#+1
\ 000000E4 FCFFFF1A BNE ??LowLevelInit_6
150 AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;
\ 000000E8 CB00E0E3 MVN R0,#+203
\ 000000EC E00EC0E3 BIC R0,R0,#0xE00
\ 000000F0 80109FE5 LDR R1,??LowLevelInit_1+0xC ;; defaultSpuriousHandler
\ 000000F4 001080E5 STR R1,[R0, #+0]
151
152 // Unstack nested interrupts
153 for (i = 0; i < 8 ; i++) {
\ 000000F8 0800A0E3 MOV R0,#+8
\ 000000FC CF10E0E3 MVN R1,#+207
\ 00000100 E01EC1E3 BIC R1,R1,#0xE00
\ 00000104 0020A0E3 MOV R2,#+0
154
155 AT91C_BASE_AIC->AIC_EOICR = 0;
\ ??LowLevelInit_7:
\ 00000108 002081E5 STR R2,[R1, #+0]
156 }
\ 0000010C 010050E2 SUBS R0,R0,#+1
\ 00000110 FCFFFF1A BNE ??LowLevelInit_7
157
158 // Enable Debug mode
159 AT91C_BASE_AIC->AIC_DCR = AT91C_AIC_DCR_PROT;
\ 00000114 080081E3 ORR R0,R1,#0x8
\ 00000118 0110A0E3 MOV R1,#+1
\ 0000011C 001080E5 STR R1,[R0, #+0]
160
161 /* Watchdog initialization
162 *************************/
163 AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
\ 00000120 BB00E0E3 MVN R0,#+187
\ 00000124 800FC0E3 BIC R0,R0,#0x200
\ 00000128 801CA0E3 MOV R1,#+32768
\ 0000012C 001080E5 STR R1,[R0, #+0]
164
165 /* Remap
166 *******/
167 BOARD_RemapRam();
\ 00000130 ........ BL BOARD_RemapRam
168
169 // Disable RTT and PIT interrupts (potential problem when program A
170 // configures RTT, then program B wants to use PIT only, interrupts
171 // from the RTT will still occur since they both use AT91C_ID_SYS)
172 AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);
\ 00000134 DF00E0E3 MVN R0,#+223
\ 00000138 800FC0E3 BIC R0,R0,#0x200
\ 0000013C 000090E5 LDR R0,[R0, #+0]
\ 00000140 C00BC0E3 BIC R0,R0,#0x30000
\ 00000144 DF10E0E3 MVN R1,#+223
\ 00000148 801FC1E3 BIC R1,R1,#0x200
\ 0000014C 000081E5 STR R0,[R1, #+0]
173 AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
\ 00000150 100081E3 ORR R0,R1,#0x10
\ 00000154 000090E5 LDR R0,[R0, #+0]
\ 00000158 8007C0E3 BIC R0,R0,#0x2000000
\ 0000015C 101081E3 ORR R1,R1,#0x10
\ 00000160 000081E5 STR R0,[R1, #+0]
174 }
\ 00000164 0050BDE8 POP {R12,LR}
\ 00000168 1EFF2FE1 BX LR ;; return
\ ??LowLevelInit_1:
\ 0000016C 0E104810 DC32 0x1048100e
\ 00000170 ........ DC32 defaultFiqHandler
\ 00000174 ........ DC32 defaultIrqHandler
\ 00000178 ........ DC32 defaultSpuriousHandler
175
Maximum stack usage in bytes:
Function .cstack
-------- -------
LowLevelInit 8
defaultFiqHandler 0
defaultIrqHandler 0
defaultSpuriousHandler 0
Section sizes:
Function/Label Bytes
-------------- -----
??defaultSpuriousHandler_0 4
??defaultFiqHandler_0 4
??defaultIrqHandler_0 4
LowLevelInit 380
392 bytes in section .text
392 bytes of CODE memory
Errors: none
Warnings: none
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