📄 board_memories.lst
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205
206 WRITE(AT91C_BASE_SDRC, SDRC_TR, sdrc_dbw | (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
\ 000001A0 540F84E3 ORR R0,R4,#0x150
\ 000001A4 4B10E0E3 MVN R1,#+75
\ 000001A8 000081E5 STR R0,[R1, #+0]
207
208 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_NORMAL_CMD); // Set Normal mode
\ 000001AC 0400C1E3 BIC R0,R1,#0x4
\ 000001B0 004080E5 STR R4,[R0, #+0]
209 pSdram[0] = 0x00000000; // Perform Normal mode
\ 000001B4 8005A0E3 MOV R0,#+536870912
\ 000001B8 0010A0E3 MOV R1,#+0
\ 000001BC 001080E5 STR R1,[R0, #+0]
210 }
\ 000001C0 1C40BDE8 POP {R2-R4,LR}
\ 000001C4 1EFF2FE1 BX LR ;; return
\ ??BOARD_ConfigureSdram_0:
\ 000001C8 ........ DC32 ??pinsSdram
\ 000001CC 59219221 DC32 0x21922159
\ 000001D0 DEDEFECA DC32 0xcafedede
\ In section .rodata, align 4
\ ??pinsSdram:
\ 00000000 0000803F00F4 DC32 1065353216, 0FFFFF400H
\ FFFF
\ 00000008 02010000 DC8 2, 1, 0, 0
\ 0000000C FFFF030000F6 DC32 262143, 0FFFFF600H
\ FFFF
\ 00000014 03010000 DC8 3, 1, 0, 0
\ 00000018 FFFF000000F8 DC32 65535, 0FFFFF800H
\ FFFF
\ 00000020 04000000 DC8 4, 0, 0, 0
211
212 //------------------------------------------------------------------------------
213 /// Configures the EBI for NandFlash access. Pins must be configured after or
214 /// before calling this function.
215 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
216 void BOARD_ConfigureNandFlash(unsigned char busWidth)
217 {
218 // Configure EBI
219 AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS3A_SMC_NandFlash;
\ BOARD_ConfigureNandFlash:
\ 00000000 7F10E0E3 MVN R1,#+127
\ 00000004 001091E5 LDR R1,[R1, #+0]
\ 00000008 081081E3 ORR R1,R1,#0x8
\ 0000000C 7F20E0E3 MVN R2,#+127
\ 00000010 001082E5 STR R1,[R2, #+0]
220
221 #define AT91C_SMC2_NWS_2 ((unsigned int) 1 << 0)
222 #define AT91C_SMC2_TDF_2_CYCLES ((unsigned int) 2 << 8)
223 #define AT91C_SMC2_BAT_8BIT ((unsigned int) 0 << 12)
224 #define AT91C_SMC2_DRP_STANDARD ((unsigned int) 0 << 15)
225 #define AT91C_SMC2_RWSETUP_0_CYCLE ((unsigned int) 0 << 24)
226 #define AT91C_SMC2_RWHOLD_1_CYCLE ((unsigned int) 1 << 28)
227
228 // Configure SMC
229 AT91C_BASE_SMC->SMC2_CSR[3] =
230 AT91C_SMC2_NWS_2 // 2 wait states required required by the NAND Flash device
231 | AT91C_SMC2_WSEN // NWS register enabled
232 | AT91C_SMC2_TDF_2_CYCLES // 2 Data Float Time Cycles required by the NAND Flash device
233 | AT91C_SMC2_BAT_8BIT // 1 8-bit device connected over the bus
234 | AT91C_SMC2_DBW_8 // 8-bit Data Bus Width
235 | AT91C_SMC2_DRP_STANDARD // Standard Read protocol required by the NAND Flash device
236 | AT91C_SMC2_ACSS_STANDARD // Standard address to chip select
237 | AT91C_SMC2_RWSETUP_0_CYCLE // 0 Read/Write Setup time required by the Nand Flash Device
238 | AT91C_SMC2_RWHOLD_1_CYCLE; // 1 Read/Write Setup time required by the ECC controller
\ 00000014 1C1082E3 ORR R1,R2,#0x1C
\ 00000018 00209FE5 LDR R2,??BOARD_ConfigureNandFlash_0 ;; 0x10004281
\ 0000001C ........ B ?Subroutine0
\ ??BOARD_ConfigureNandFlash_0:
\ 00000020 81420010 DC32 0x10004281
239
240 if (busWidth == 8) {
241 AT91C_BASE_SMC->SMC2_CSR[3] |= AT91C_SMC2_DBW_8;
242 }
243 else if (busWidth == 16) {
244
245 AT91C_BASE_SMC->SMC2_CSR[3] |= AT91C_SMC2_DBW_16;
246 }
247 }
\ In section .text, align 4, keep-with-next
\ ?Subroutine0:
\ 00000000 002081E5 STR R2,[R1, #+0]
\ 00000004 080050E3 CMP R0,#+8
\ 00000008 00009105 LDREQ R0,[R1, #+0]
\ 0000000C 400C8003 ORREQ R0,R0,#0x4000
\ 00000010 00008105 STREQ R0,[R1, #+0]
\ 00000014 1EFF2F01 BXEQ LR
\ 00000018 100050E3 CMP R0,#+16
\ 0000001C 00009105 LDREQ R0,[R1, #+0]
\ 00000020 800D8003 ORREQ R0,R0,#0x2000
\ 00000024 00008105 STREQ R0,[R1, #+0]
\ 00000028 1EFF2FE1 BX LR ;; return
\ ??Subroutine0_0:
\ 0000002C 82010021 DC32 0x21000182
248
249 //------------------------------------------------------------------------------
250 /// Configures a list of AT91S_EFC instances.
251 /// \param list Pointer to a list of AT91S_EFC instances.
252 /// \param size Size of the AT91S_EFC list.
253 /// \param numWaitStates Number of state cycles value for the EFC.
254 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
255 void BOARD_ConfigureFlash48MHz(void)
256 {
257 /* Set flash wait states in the EFC
258 **********************************/
259 /* 48MHz = 1 wait state */
260 #if defined(at91sam7se512)
261 AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_2FWS;
\ BOARD_ConfigureFlash48MHz:
\ 00000000 9F00E0E3 MVN R0,#+159
\ 00000004 801FA0E3 MOV R1,#+512
\ 00000008 001080E5 STR R1,[R0, #+0]
262 AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_2FWS;
\ 0000000C 100080E3 ORR R0,R0,#0x10
\ 00000010 001080E5 STR R1,[R0, #+0]
263 #elif defined(at91sam7se32) || defined(at91sam7se256)
264 AT91C_BASE_EFC->EFC_FMR = AT91C_MC_FWS_2FWS;
265 #else
266 #error No chip definition ?
267 #endif
268 }
\ 00000014 1EFF2FE1 BX LR ;; return
269
270 //------------------------------------------------------------------------------
271 /// Configures the EBI for NorFlash access at 48MHz.
272 /// \Param busWidth Bus width
273 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
274 void BOARD_ConfigureNorFlash(unsigned char busWidth)
275 {
276
277 // Configure SMC
278 AT91C_BASE_SMC->SMC2_CSR[0] =
279 ((unsigned int) 2 << 0) // 2 wait states required required by the NOR Flash device
280 | AT91C_SMC2_WSEN // NWS register enabled
281 | ((unsigned int) 1 << 8) // 1 Data Float Time Cycles required by the NOR Flash device
282 | AT91C_SMC2_BAT_8BIT // 1 8-bit device connected over the bus
283 | AT91C_SMC2_DRP_STANDARD // Standard Read protocol required by the NOR Flash device
284 | ((unsigned int) 1 << 24) // 1 Read/Write Setup time required by the NOR Flash Device
285 | ((unsigned int) 2 << 28); // 2 Read/Write Setup time required by the ECC controller
\ BOARD_ConfigureNorFlash:
\ 00000000 6F10E0E3 MVN R1,#+111
\ 00000004 ........ LDR R2,??Subroutine0_0 ;; 0x21000182
\ 00000008 REQUIRE ?Subroutine0
\ 00000008 ;; // Fall through to label ?Subroutine0
286 if (busWidth == 8) {
287 AT91C_BASE_SMC->SMC2_CSR[0] |= AT91C_SMC2_DBW_8;
288 }
289 else if (busWidth == 16) {
290
291 AT91C_BASE_SMC->SMC2_CSR[0] |= AT91C_SMC2_DBW_16;
292 }
293 }
294
Maximum stack usage in bytes:
Function .cstack
-------- -------
BOARD_ConfigureFlash48MHz 0
BOARD_ConfigureNandFlash 0
BOARD_ConfigureNorFlash 0
BOARD_ConfigureSdram 16
BOARD_GetRemap 0
BOARD_RemapFlash 8
BOARD_RemapRam 8
Section sizes:
Function/Label Bytes
-------------- -----
BOARD_GetRemap 56
BOARD_RemapFlash 16
?Subroutine1 20
BOARD_RemapRam 12
BOARD_ConfigureSdram 468
pinsSdram 36
BOARD_ConfigureNandFlash 36
?Subroutine0 48
BOARD_ConfigureFlash48MHz 24
BOARD_ConfigureNorFlash 8
36 bytes in section .rodata
688 bytes in section .text
688 bytes of CODE memory
36 bytes of CONST memory
Errors: none
Warnings: 1
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