📄 board_memories.lst
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116 /// Initializes the SDRAM controller so the external SDRAM chip connected to the
117 /// EBI is accessible. The EBI pins for the SDRAM must be configured prior to
118 /// calling this function.
119 //------------------------------------------------------------------------------
\ In section .text, align 4, keep-with-next
120 void BOARD_ConfigureSdram(unsigned char busWidth)
121 {
\ BOARD_ConfigureSdram:
\ 00000000 13402DE9 PUSH {R0,R1,R4,LR}
122 volatile unsigned int i;
123 static const Pin pinsSdram[] = {PINS_SDRAM};
124 volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
125 unsigned short sdrc_dbw = 0;
126
127 switch (busWidth) {
\ 00000004 200050E3 CMP R0,#+32
128 case 16:
129 default:
130 sdrc_dbw = AT91C_SDRC_DBW_16_BITS;
\ 00000008 1040A013 MOVNE R4,#+16
131 break;
132
133 case 32:
134 sdrc_dbw = AT91C_SDRC_DBW_32_BITS;
\ 0000000C 0040A003 MOVEQ R4,#+0
135 break;
136
137 }
138
139
140 // Enable corresponding PIOs
141 PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));
\ 00000010 0310A0E3 MOV R1,#+3
\ 00000014 AC019FE5 LDR R0,??BOARD_ConfigureSdram_0 ;; ??pinsSdram
\ 00000018 ........ BL PIO_Configure
142
143 // Enable EBI chip select for the SDRAM
144 WRITE(AT91C_BASE_EBI, EBI_CSA, AT91C_EBI_CS1A_SDRAMC);
\ 0000001C 7F00E0E3 MVN R0,#+127
\ 00000020 0210A0E3 MOV R1,#+2
\ 00000024 001080E5 STR R1,[R0, #+0]
145
146 #define AT91C_SDRC_NC_9 (0x1)
147 #define AT91C_SDRC_NR_13 (0x2 << 2)
148 #define AT91C_SDRC_CAS_2 (0x2 << 5)
149 #define AT91C_SDRC_NB_4_BANKS (0x1 << 4)
150 #define AT91C_SDRC_TWR_2 (0x2 << 7)
151 #define AT91C_SDRC_TRC_4 (0x4 << 11)
152 #define AT91C_SDRC_TRP_4 (0x4 << 15)
153 #define AT91C_SDRC_TRCD_2 (0x2 << 19)
154 #define AT91C_SDRC_TRAS_3 (0x3 << 23)
155 #define AT91C_SDRC_TXSR_4 (0x4 << 27)
156
157 // CFG Control Register
158 WRITE(AT91C_BASE_SDRC, SDRC_CR, AT91C_SDRC_NC_9
159 | AT91C_SDRC_NR_13
160 | AT91C_SDRC_CAS_2
161 | AT91C_SDRC_NB_4_BANKS
162 | AT91C_SDRC_TWR_2
163 | AT91C_SDRC_TRC_4
164 | AT91C_SDRC_TRP_4
165 | AT91C_SDRC_TRCD_2
166 | AT91C_SDRC_TRAS_3
167 | AT91C_SDRC_TXSR_4);
\ 00000028 380080E3 ORR R0,R0,#0x38
\ 0000002C 98119FE5 LDR R1,??BOARD_ConfigureSdram_0+0x4 ;; 0x21922159
\ 00000030 001080E5 STR R1,[R0, #+0]
168
169 for (i = 0; i < 1000; i++);
\ 00000034 0010A0E3 MOV R1,#+0
\ 00000038 00108DE5 STR R1,[SP, #+0]
\ 0000003C 020000EA B ??BOARD_ConfigureSdram_1
\ ??BOARD_ConfigureSdram_2:
\ 00000040 00009DE5 LDR R0,[SP, #+0]
\ 00000044 010080E2 ADD R0,R0,#+1
\ 00000048 00008DE5 STR R0,[SP, #+0]
\ ??BOARD_ConfigureSdram_1:
\ 0000004C 00009DE5 LDR R0,[SP, #+0]
\ 00000050 FA0F50E3 CMP R0,#+1000
\ 00000054 F9FFFF3A BCC ??BOARD_ConfigureSdram_2
170
171 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_NOP_CMD); // Perform NOP
\ 00000058 010084E3 ORR R0,R4,#0x1
\ 0000005C 4F10E0E3 MVN R1,#+79
\ 00000060 000081E5 STR R0,[R1, #+0]
172 pSdram[0] = 0x00000000;
\ 00000064 8005A0E3 MOV R0,#+536870912
\ 00000068 0010A0E3 MOV R1,#+0
\ 0000006C 001080E5 STR R1,[R0, #+0]
173
174 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_PRCGALL_CMD); // Set PRCHG AL
\ 00000070 020084E3 ORR R0,R4,#0x2
\ 00000074 4F10E0E3 MVN R1,#+79
\ 00000078 000081E5 STR R0,[R1, #+0]
175 pSdram[0] = 0x00000000; // Perform PRCHG
\ 0000007C 8005A0E3 MOV R0,#+536870912
\ 00000080 0010A0E3 MOV R1,#+0
\ 00000084 001080E5 STR R1,[R0, #+0]
176
177 for (i = 0; i < 10000; i++);
\ 00000088 00108DE5 STR R1,[SP, #+0]
\ 0000008C 1010A0E3 MOV R1,#+16
\ 00000090 9C1D81E3 ORR R1,R1,#0x2700
\ 00000094 020000EA B ??BOARD_ConfigureSdram_3
\ ??BOARD_ConfigureSdram_4:
\ 00000098 00009DE5 LDR R0,[SP, #+0]
\ 0000009C 010080E2 ADD R0,R0,#+1
\ 000000A0 00008DE5 STR R0,[SP, #+0]
\ ??BOARD_ConfigureSdram_3:
\ 000000A4 00009DE5 LDR R0,[SP, #+0]
\ 000000A8 010050E1 CMP R0,R1
\ 000000AC F9FFFF3A BCC ??BOARD_ConfigureSdram_4
178
179 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 1st CBR
\ 000000B0 040084E3 ORR R0,R4,#0x4
\ 000000B4 4F10E0E3 MVN R1,#+79
\ 000000B8 000081E5 STR R0,[R1, #+0]
180 pSdram[1] = 0x00000001; // Perform CBR
\ 000000BC 4202A0E3 MOV R0,#+536870916
\ 000000C0 0110A0E3 MOV R1,#+1
\ 000000C4 001080E5 STR R1,[R0, #+0]
181
182 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 2 CBR
\ 000000C8 040084E3 ORR R0,R4,#0x4
\ 000000CC 4F10E0E3 MVN R1,#+79
\ 000000D0 000081E5 STR R0,[R1, #+0]
183 pSdram[2] = 0x00000002; // Perform CBR
\ 000000D4 8202A0E3 MOV R0,#+536870920
\ 000000D8 0210A0E3 MOV R1,#+2
\ 000000DC 001080E5 STR R1,[R0, #+0]
184
185 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 3 CBR
\ 000000E0 040084E3 ORR R0,R4,#0x4
\ 000000E4 4F10E0E3 MVN R1,#+79
\ 000000E8 000081E5 STR R0,[R1, #+0]
186 pSdram[3] = 0x00000003; // Perform CBR
\ 000000EC C202A0E3 MOV R0,#+536870924
\ 000000F0 0310A0E3 MOV R1,#+3
\ 000000F4 001080E5 STR R1,[R0, #+0]
187
188 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 4 CBR
\ 000000F8 040084E3 ORR R0,R4,#0x4
\ 000000FC 4F10E0E3 MVN R1,#+79
\ 00000100 000081E5 STR R0,[R1, #+0]
189 pSdram[4] = 0x00000004; // Perform CBR
\ 00000104 1000A0E3 MOV R0,#+16
\ 00000108 800580E3 ORR R0,R0,#0x20000000
\ 0000010C 0410A0E3 MOV R1,#+4
\ 00000110 001080E5 STR R1,[R0, #+0]
190
191 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 5 CBR
\ 00000114 040084E3 ORR R0,R4,#0x4
\ 00000118 4F10E0E3 MVN R1,#+79
\ 0000011C 000081E5 STR R0,[R1, #+0]
192 pSdram[5] = 0x00000005; // Perform CBR
\ 00000120 1400A0E3 MOV R0,#+20
\ 00000124 800580E3 ORR R0,R0,#0x20000000
\ 00000128 0510A0E3 MOV R1,#+5
\ 0000012C 001080E5 STR R1,[R0, #+0]
193
194 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 6 CBR
\ 00000130 040084E3 ORR R0,R4,#0x4
\ 00000134 4F10E0E3 MVN R1,#+79
\ 00000138 000081E5 STR R0,[R1, #+0]
195 pSdram[6] = 0x00000006; // Perform CBR
\ 0000013C 1800A0E3 MOV R0,#+24
\ 00000140 800580E3 ORR R0,R0,#0x20000000
\ 00000144 0610A0E3 MOV R1,#+6
\ 00000148 001080E5 STR R1,[R0, #+0]
196
197 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 7 CBR
\ 0000014C 040084E3 ORR R0,R4,#0x4
\ 00000150 4F10E0E3 MVN R1,#+79
\ 00000154 000081E5 STR R0,[R1, #+0]
198 pSdram[7] = 0x00000007; // Perform CBR
\ 00000158 1C00A0E3 MOV R0,#+28
\ 0000015C 800580E3 ORR R0,R0,#0x20000000
\ 00000160 0710A0E3 MOV R1,#+7
\ 00000164 001080E5 STR R1,[R0, #+0]
199
200 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_RFSH_CMD); // Set 8 CBR
\ 00000168 040084E3 ORR R0,R4,#0x4
\ 0000016C 4F10E0E3 MVN R1,#+79
\ 00000170 000081E5 STR R0,[R1, #+0]
201 pSdram[8] = 0x00000008; // Perform CBR
\ 00000174 2000A0E3 MOV R0,#+32
\ 00000178 800580E3 ORR R0,R0,#0x20000000
\ 0000017C 0810A0E3 MOV R1,#+8
\ 00000180 001080E5 STR R1,[R0, #+0]
202
203 WRITE(AT91C_BASE_SDRC, SDRC_MR, sdrc_dbw | AT91C_SDRC_MODE_LMR_CMD); // Set LMR operation
\ 00000184 030084E3 ORR R0,R4,#0x3
\ 00000188 4F10E0E3 MVN R1,#+79
\ 0000018C 000081E5 STR R0,[R1, #+0]
204 pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
\ 00000190 2400A0E3 MOV R0,#+36
\ 00000194 800580E3 ORR R0,R0,#0x20000000
\ 00000198 30109FE5 LDR R1,??BOARD_ConfigureSdram_0+0x8 ;; 0xcafedede
\ 0000019C 001080E5 STR R1,[R0, #+0]
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