my_uart_top.map.qmsg

很好用的串口通讯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 26 15:26:48 2009 " "Info: Processing started: Thu Feb 26 15:26:48 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off my_uart_top -c my_uart_top --generate_symbol=\"D:\\Nios II资料\\RS232\\RS232\\uartverilog\\speed_select.v\" " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off my_uart_top -c my_uart_top --generate_symbol=\"D:\\Nios II资料\\RS232\\RS232\\uartverilog\\speed_select.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "EQSYN_NO_QID_SUPPORT" "MAX II " "Error: Analysis and Synthesis does not support Full Incremental Compilation for device family MAX II" {  } {  } 0 0 "Analysis and Synthesis does not support Full Incremental Compilation for device family %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Thu Feb 26 15:26:49 2009 " "Error: Processing ended: Thu Feb 26 15:26:49 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}