rs232_trans.v

controller for sending serial data at different speeds

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    10:18:53 12/01/05
// Design Name:    
// Module Name:    Rs232_Trans
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision: Cambiado a Sincronico, clk de 50Mhz...
// Revision 0.01 - File Created
// Additional Comments: // Basado en la version de fpga4fun...
// 
////////////////////////////////////////////////////////////////////////////////
module Rs232_Trans(TxD, TxD_ready, Clk, TxD_start, TxD_data, parity);
input Clk, TxD_start, parity;
input [7:0] TxD_data;
output TxD, TxD_ready;

reg TxD,parityD;
reg [9:0] BaudDivCnt = 0;
reg [3:0] state = 0;
reg [7:0] TxD_dataD;
reg Baud;

assign TxD_ready = (state == 0) && ~TxD_start;
//assign Baud = BaudDivCnt[8] && BaudDivCnt[7] && BaudDivCnt[5] && BaudDivCnt[4] && BaudDivCnt[1]; // 50M / 434 = 115207.37

	
always @(posedge Clk) begin
	if (Baud) begin
		BaudDivCnt <= 0;
		Baud <= 0;
	end
	else if (BaudDivCnt == 10'b1101100100)
		Baud <= 1;
	else
		BaudDivCnt <= BaudDivCnt + 1;
end

always @(negedge Clk) begin
	case(state)
		4'd0:
		begin
			if (TxD_start) begin
				TxD_dataD = TxD_data;
				parityD = parity;
				state = state + 1;
			end 
			else begin
				TxD = 1; // Line Available
				state = 0;
			end
		end
		4'd1:
		begin
			if (Baud) begin
			TxD = 0; // Start bit?
			state = state + 1;
			end
		end
		4'd2, 
		4'd3, 
		4'd4, 
		4'd5, 
		4'd6, 
		4'd7, 
		4'd8,
		4'd9:
		begin
			if (Baud) begin
			TxD = TxD_dataD[0];
			TxD_dataD = TxD_dataD >> 1;
			state = state + 1;
			end
		end
		4'd10:
		begin
			if (Baud) begin
			TxD = parityD;
			state = state + 1;
			end
		end
		4'd11:
		begin
			if (Baud) begin
			TxD = 1;
			state = 0;
			end
		end
		default:
		begin
			TxD = 1;
			state = 0;
		end
	endcase
end

endmodule