📄 test.lst
字号:
00F2 157 _BREG_F2 = 0x00f2
00F3 158 _BREG_F3 = 0x00f3
00F4 159 _BREG_F4 = 0x00f4
00F5 160 _BREG_F5 = 0x00f5
00F6 161 _BREG_F6 = 0x00f6
00F7 162 _BREG_F7 = 0x00f7
163 ;--------------------------------------------------------
164 ; overlayable register banks
165 ;--------------------------------------------------------
166 .area REG_BANK_0 (REL,OVR,DATA)
0000 167 .ds 8
168 ;--------------------------------------------------------
169 ; internal ram data
170 ;--------------------------------------------------------
171 .area DSEG (DATA)
172 ;--------------------------------------------------------
173 ; overlayable items in internal ram
174 ;--------------------------------------------------------
175 .area OSEG (OVR,DATA)
176 ;--------------------------------------------------------
177 ; Stack segment in internal ram
178 ;--------------------------------------------------------
179 .area SSEG (DATA)
0000 180 __start__stack:
0000 181 .ds 1
182
183 ;--------------------------------------------------------
184 ; indirectly addressable internal ram data
185 ;--------------------------------------------------------
186 .area ISEG (DATA)
187 ;--------------------------------------------------------
188 ; bit data
189 ;--------------------------------------------------------
190 .area BSEG (BIT)
0090 191 _SCK = 0x0090
0091 192 _SDA = 0x0091
193 ;--------------------------------------------------------
194 ; external ram data
195 ;--------------------------------------------------------
196 .area XSEG (XDATA)
197 ;--------------------------------------------------------
198 ; external initialized ram data
199 ;--------------------------------------------------------
200 .area XISEG (XDATA)
201 ;--------------------------------------------------------
202 ; interrupt vector
203 ;--------------------------------------------------------
204 .area CSEG (CODE)
0000 205 __interrupt_vect:
0000 02s00r00 206 ljmp __sdcc_gsinit_startup
0003 32 207 reti
0004 208 .ds 7
000B 32 209 reti
000C 210 .ds 7
0013 32 211 reti
0014 212 .ds 7
001B 32 213 reti
001C 214 .ds 7
0023 32 215 reti
0024 216 .ds 7
002B 32 217 reti
002C 218 .ds 7
219 ;--------------------------------------------------------
220 ; global & static initialisations
221 ;--------------------------------------------------------
222 .area GSINIT (CODE)
223 .area GSFINAL (CODE)
224 .area GSINIT (CODE)
0000 225 __sdcc_gsinit_startup:
0000 75 81rFF 226 mov sp,#__start__stack - 1
0003 12s00r00 227 lcall __sdcc_external_startup
0006 E5 82 228 mov a,dpl
0008 60 03 229 jz __sdcc_init_data
000A 02s00r33 230 ljmp __sdcc_program_startup
000D 231 __sdcc_init_data:
232 ; _mcs51_genXINIT() start
000D 74r00 233 mov a,#l_XINIT
000F 44s00 234 orl a,#l_XINIT>>8
0011 60 29 235 jz 00003$
0013 74r00 236 mov a,#s_XINIT
0015 24r00 237 add a,#l_XINIT
0017 F9 238 mov r1,a
0018 74s00 239 mov a,#s_XINIT>>8
001A 34s00 240 addc a,#l_XINIT>>8
001C FA 241 mov r2,a
001D 90s00r00 242 mov dptr,#s_XINIT
0020 78r00 243 mov r0,#s_XISEG
0022 75 A0s00 244 mov p2,#(s_XISEG >> 8)
0025 E4 245 00001$: clr a
0026 93 246 movc a,@a+dptr
0027 F2 247 movx @r0,a
0028 A3 248 inc dptr
0029 08 249 inc r0
002A B8 00 02 250 cjne r0,#0,00002$
002D 05 A0 251 inc p2
002F E5 82 252 00002$: mov a,dpl
0031 B5 01 F1 253 cjne a,ar1,00001$
0034 E5 83 254 mov a,dph
0036 B5 02 EC 255 cjne a,ar2,00001$
0039 75 A0 FF 256 mov p2,#0xFF
003C 257 00003$:
258 ; _mcs51_genXINIT() end
259 .area GSFINAL (CODE)
0000 02s00r33 260 ljmp __sdcc_program_startup
261 ;--------------------------------------------------------
262 ; Home
263 ;--------------------------------------------------------
264 .area HOME (CODE)
265 .area CSEG (CODE)
266 ;--------------------------------------------------------
267 ; code
268 ;--------------------------------------------------------
269 .area CSEG (CODE)
0033 270 __sdcc_program_startup:
0033 12s00r38 271 lcall _main
272 ; return from main will lock up
0036 80 FE 273 sjmp .
274 ;------------------------------------------------------------
275 ;Allocation info for local variables in function 'main'
276 ;------------------------------------------------------------
277 ;------------------------------------------------------------
278 ;C:/Maxx/Proyectos/APublicar/test.c:61: void main (void)
279 ; -----------------------------------------
280 ; function main
281 ; -----------------------------------------
0038 282 _main:
0002 283 ar2 = 0x02
0003 284 ar3 = 0x03
0004 285 ar4 = 0x04
0005 286 ar5 = 0x05
0006 287 ar6 = 0x06
0007 288 ar7 = 0x07
0000 289 ar0 = 0x00
0001 290 ar1 = 0x01
291 ;C:/Maxx/Proyectos/APublicar/test.c:63: weeprom (0x01,0xF0, 0x50);
292 ; genAssign
0038 75*00 F0 293 mov _weeprom_PARM_2,#0xF0
294 ; genAssign
003B 75*00 50 295 mov _weeprom_PARM_3,#0x50
296 ; genCall
003E 75 82 01 297 mov dpl,#0x01
0041 12s00r00 298 lcall _weeprom
299 ;C:/Maxx/Proyectos/APublicar/test.c:65: do
0044 300 00101$:
301 ;C:/Maxx/Proyectos/APublicar/test.c:66: P3++;
302 ; genPlus
303 ; genPlusIncr
0044 05 B0 304 inc _P3
305 ;C:/Maxx/Proyectos/APublicar/test.c:67: while (1);
306 ; Peephole 132 changed ljmp to sjmp
0046 80 FC 307 sjmp 00101$
0048 308 00104$:
0048 22 309 ret
310 .area CSEG (CODE)
311 .area XINIT (CODE)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -