📄 wave_generator.fit.rpt
字号:
Fitter report for wave_generator
Wed Mar 18 20:49:23 2009
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Input Pins
7. Output Pins
8. All Package Pins
9. Control Signals
10. Carry Chains
11. Embedded Cells
12. Non-Global High Fan-Out Signals
13. LAB
14. Local Routing Interconnect
15. LAB External Interconnect
16. Row Interconnect
17. LAB Column Interconnect
18. LAB Column Interconnect
19. Fitter Resource Usage Summary
20. Fitter Resource Utilization by Entity
21. Delay Chain Summary
22. Fitter RAM Summary
23. Pin-Out File
24. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Wed Mar 18 20:49:23 2009 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; wave_generator ;
; Top-level Entity Name ; wave_generator ;
; Family ; FLEX10K ;
; Device ; EPF10K10LC84-4 ;
; Timing Models ; Final ;
; Total logic elements ; 24 / 576 ( 4 % ) ;
; Total pins ; 10 / 59 ( 16 % ) ;
; Total memory bits ; 2,048 / 6,144 ( 33 % ) ;
+-----------------------+------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+--------------------+--------------------+
; Device ; EPF10K10LC84-4 ; ;
; Use smart compilation ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Logic Cell Insertion - Individual Logic Cells ; On ; On ;
; Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains ; On ; On ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Auto Global Clock ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/zbl/wave_generator.fit.eqn.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
; Name ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; Single-Pin CE ; I/O Standard ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
; var ; 29 ; C ; -- ; 8 ; no ; no ; no ; no ; no ; TTL ;
; clk ; 16 ; A ; -- ; 8 ; no ; no ; no ; no ; no ; TTL ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+---------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+---------------+--------------+
; Name ; Pin # ; Row ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ;
+---------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+---------------+--------------+
; data[7] ; 58 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[6] ; 59 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[5] ; 60 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[4] ; 61 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[3] ; 62 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[2] ; 64 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[1] ; 65 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
; data[0] ; 66 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; yes ; TTL ;
+---------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+---------------+--------------+
+-----------------------------------+
; All Package Pins ;
+-------+------------+--------------+
; Pin # ; Usage ; I/O Standard ;
+-------+------------+--------------+
; 1 ; GND+ ; ;
; 2 ; GND+ ; ;
; 3 ; GND* ; ;
; 4 ; VCC_INT ; ;
; 5 ; GND* ; ;
; 6 ; GND* ; ;
; 7 ; GND* ; ;
; 8 ; GND* ; ;
; 9 ; GND* ; ;
; 10 ; GND* ; ;
; 11 ; GND* ; ;
; 12 ; ^DATA0 ; ;
; 13 ; ^DCLK ; ;
; 14 ; ^nCE ; ;
; 15 ; #TDI ; ;
; 16 ; clk ; TTL ;
; 17 ; GND* ; ;
; 18 ; GND* ; ;
; 19 ; GND* ; ;
; 20 ; VCC_INT ; ;
; 21 ; GND* ; ;
; 22 ; GND* ; ;
; 23 ; GND* ; ;
; 24 ; GND* ; ;
; 25 ; GND* ; ;
; 26 ; GND_INT ; ;
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