wave_generator.tan.rpt

用LPM_ROM设计存放一个周期的256×8大小的rom,构建简易频率可控的正弦波发生器。

; N/A   ; None         ; 40.200 ns  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data[2] ; clk        ;
; N/A   ; None         ; 40.200 ns  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; data[2] ; clk        ;
; N/A   ; None         ; 40.100 ns  ; address:inst1|data1[0]                                                    ; data[0] ; clk        ;
; N/A   ; None         ; 40.100 ns  ; address:inst1|data1[0]                                                    ; data[1] ; clk        ;
; N/A   ; None         ; 40.100 ns  ; address:inst1|data1[0]                                                    ; data[2] ; clk        ;
+-------+--------------+------------+---------------------------------------------------------------------------+---------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                    ;
+---------------+-------------+-----------+------+---------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                                                                        ; To Clock ;
+---------------+-------------+-----------+------+---------------------------------------------------------------------------+----------+
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clk      ;
; N/A           ; None        ; 0.800 ns  ; var  ; address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; clk      ;
; N/A           ; None        ; -3.200 ns ; var  ; address:inst1|data1[0]                                                    ; clk      ;
+---------------+-------------+-----------+------+---------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Mar 18 20:49:28 2009
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off wave_generator -c wave_generator
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 72.46 MHz between source register "address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[6]" (period= 13.8 ns)
    Info: + Longest register to register delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B2; Fanout = 13; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(2.300 ns) + CELL(1.200 ns) = 3.500 ns; Loc. = LC2_B3; Fanout = 2; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC3_B3; Fanout = 2; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC4_B3; Fanout = 2; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC5_B3; Fanout = 2; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC6_B3; Fanout = 2; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC7_B3; Fanout = 1; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 8: + IC(0.000 ns) + CELL(1.300 ns) = 6.300 ns; Loc. = LC8_B3; Fanout = 1; COMB Node = 'address:inst1|lpm_add_sub:add_rtl_1|addcore:adder|unreg_res_node[7]'
        Info: 9: + IC(2.200 ns) + CELL(1.700 ns) = 10.200 ns; Loc. = LC7_B2; Fanout = 10; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[6]'
        Info: Total cell delay = 5.700 ns ( 55.88 % )
        Info: Total interconnect delay = 4.500 ns ( 44.12 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 10.400 ns
            Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_16; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(6.900 ns) + CELL(0.000 ns) = 10.400 ns; Loc. = LC7_B2; Fanout = 10; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[6]'
            Info: Total cell delay = 3.500 ns ( 33.65 % )
            Info: Total interconnect delay = 6.900 ns ( 66.35 % )
        Info: - Longest clock path from clock "clk" to source register is 10.400 ns
            Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_16; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(6.900 ns) + CELL(0.000 ns) = 10.400 ns; Loc. = LC1_B2; Fanout = 13; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 3.500 ns ( 33.65 % )
            Info: Total interconnect delay = 6.900 ns ( 66.35 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "address:inst1|data1[0]" (data pin = "var", clock pin = "clk") is 7.300 ns
    Info: + Longest pin to register delay is 15.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 14; PIN Node = 'var'
        Info: 2: + IC(6.500 ns) + CELL(1.800 ns) = 11.800 ns; Loc. = LC8_B2; Fanout = 1; COMB Node = 'address:inst1|data1[0]~12'
        Info: 3: + IC(2.200 ns) + CELL(1.200 ns) = 15.200 ns; Loc. = LC1_B3; Fanout = 10; REG Node = 'address:inst1|data1[0]'
        Info: Total cell delay = 6.500 ns ( 42.76 % )
        Info: Total interconnect delay = 8.700 ns ( 57.24 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "clk" to destination register is 10.400 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_16; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(6.900 ns) + CELL(0.000 ns) = 10.400 ns; Loc. = LC1_B3; Fanout = 10; REG Node = 'address:inst1|data1[0]'
        Info: Total cell delay = 3.500 ns ( 33.65 % )
        Info: Total interconnect delay = 6.900 ns ( 66.35 % )
Info: tco from clock "clk" to destination pin "data[3]" through register "address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" is 41.400 ns
    Info: + Longest clock path from clock "clk" to source register is 10.400 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_16; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(6.900 ns) + CELL(0.000 ns) = 10.400 ns; Loc. = LC1_B2; Fanout = 13; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 3.500 ns ( 33.65 % )
        Info: Total interconnect delay = 6.900 ns ( 66.35 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 29.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B2; Fanout = 13; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(2.500 ns) + CELL(12.600 ns) = 15.100 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]~mem_cell_ra0'
        Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 17.600 ns; Loc. = EC4_B; Fanout = 1; MEM Node = 'lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]'
        Info: 4: + IC(3.800 ns) + CELL(1.800 ns) = 23.200 ns; Loc. = LC1_C23; Fanout = 1; COMB Node = 'data[3]~4'
        Info: 5: + IC(1.600 ns) + CELL(5.100 ns) = 29.900 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'data[3]'
        Info: Total cell delay = 22.000 ns ( 73.58 % )
        Info: Total interconnect delay = 7.900 ns ( 26.42 % )
Info: th for register "address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" (data pin = "var", clock pin = "clk") is 0.800 ns
    Info: + Longest clock path from clock "clk" to destination register is 10.400 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_16; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(6.900 ns) + CELL(0.000 ns) = 10.400 ns; Loc. = LC1_B2; Fanout = 13; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 3.500 ns ( 33.65 % )
        Info: Total interconnect delay = 6.900 ns ( 66.35 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 11.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_29; Fanout = 14; PIN Node = 'var'
        Info: 2: + IC(6.500 ns) + CELL(1.200 ns) = 11.200 ns; Loc. = LC1_B2; Fanout = 13; REG Node = 'address:inst1|lpm_counter:data1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 4.700 ns ( 41.96 % )
        Info: Total interconnect delay = 6.500 ns ( 58.04 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Mar 18 20:49:30 2009
    Info: Elapsed time: 00:00:03