address.vhd

来自「用LPM_ROM设计存放一个周期的256×8大小的rom,构建简易频率可控的正弦」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity address is port(
	clk:	in std_logic;
	var:    in std_logic;
	data:	out std_logic_vector(7 downto 0));
end entity address;

architecture depict of address is
	signal data1:	std_logic_vector(7 downto 0):="00000000";	
begin
	p1:process(clk,var)
	begin
		if(rising_edge(clk)) then
		    if(var='0')then
			data1 <= data1 + 1;
			else
			data1 <= data1 + 2;
			end if;	
		end if;
	end process p1;
	data <= data1;
end depict;