csl_dma.h

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/** @mainpage DMA CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for the
 * DMA module across various devices. The CSL developer is expected to refer to
 * this document while designing APIs for these modules. Some of the listed APIs
 * may not be applicable to a given DMA module. While in other cases this list
 * of APIs may not be sufficient to cover all the features of a particular DMA
 * Module. The CSL developer should use his discretion in designing new APIs or
 * extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.03
 *    -# MGS3_401, Megastar3 Generic DMA Functional Specification, Version 1.1
 *
 */

/** @file csl_dpll.h
 *
 *  @brief    Header file for functional layer of CSL
 *
 *  Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 *  Modification 3
 *    - modified on: 25/01/2005
 *    - reason: Renamed RHEA to TIPB.
 *              Added generic sync events.
 * 
 *  @date 25th Jan, 2005
 *  @author S Prasad.
 *
 *  Modification 2
 *    - modified on: 30/03/2004
 *    - reason: Doxygenation of the comments to enable document generation
 *
 *  Modification 1
 *    - modified on: 29/03/2004
 *    - reason: Created the initail file from OMAP5905 CSL release on 7th Oct 2003
 *
 *  @date 29th March, 2004
 *  @author Prakash V. Gudnavar.
 */

#ifndef _CSL_DMA_H_
#define _CSL_DMA_H_

#ifdef __cplusplus
extern "C" {
#endif


#include <csl.h>
#include <cslr_dma.h>

/**************************************************************************\
* DMA global typedef declarations
\**************************************************************************/

/** @brief DMA channel instances */
/** Channel 0 */
#define CSL_DMA_CHA0         0
/** Channel 1 */
#define CSL_DMA_CHA1         1
/** Channel 2 */
#define CSL_DMA_CHA2         2
/** Channel 3 */
#define CSL_DMA_CHA3         3
/** Channel 4 */
#define CSL_DMA_CHA4         4
/** Channel 5 */
#define CSL_DMA_CHA5         5

/** @brief Enumerations for Burst enable/disable
 */
typedef enum {
    /** Burst disabled */
    CSL_DMA_BURSTEN_DISABLE    =              0,
    /** Burst enabled */
    CSL_DMA_BURSTEN_ENABLE     =              2
} CSL_DmaBurstEn;

/** @brief Enumerations for Type of port
 *
 * This enumeration is used to select source/destination port.
 */
typedef enum {
    /** SARAM port */
    CSL_DMA_PORT_SARAM         =              0,
    /** DARAM port */
    CSL_DMA_PORT_DARAM         =              1,
    /** EMIF port */
    CSL_DMA_PORT_EMIF          =              2,
    /** TIPB port */
    CSL_DMA_PORT_TIPB          =              3
} CSL_DmaPort;

/** @brief Enumerations for Addressing mode
 *
 * This enumeration is used to select addressing mode.
 */
typedef enum {
    /** Constant addressing mode */
    CSL_DMA_AMODE_CONST        =              0,
    /** Post increment addressing mode */
    CSL_DMA_AMODE_POSTINC      =              1,
    /** Single indexed addressing mode */
    CSL_DMA_AMODE_SNGLIND      =              2,
    /** Double indexed addressing mode */
    CSL_DMA_AMODE_DBLIND       =              3
} CSL_DmaAmode;

/** @brief Enumerations for Element size
 *
 * This enumeration is used to select the element size.
 */
typedef enum {
    /** Element size 8 bits */
    CSL_DMA_DATASIZE_8BIT      =              0,
    /** Element size 16 bits */
    CSL_DMA_DATASIZE_16BIT     =              1,
    /** Element size 32 bits */
    CSL_DMA_DATASIZE_32BIT     =              2
} CSL_DmaDataSize;

/** @brief Enumerations for Priority of channel
 *
 * This enumeration is used to select the priority of transfer.
 */
typedef enum {
    /** Low priority transfer */
    CSL_DMA_PRIORITY_LO        =              0,
    /** High priority transfer */
    CSL_DMA_PRIORITY_HI        =              1
} CSL_DmaPriority;

/** @brief Enumerations for Hardware synchronization
 *
 * This enumeration is used to select the hardware synchronization for data
 * transfers.
 */
typedef enum {
    /** Channel not synchronized on request */
    CSL_DMA_SYNC_NONE           =       0,
    /** Channel synchronized on MCSI_1 Transmit (handler default) */
    CSL_DMA_SYNC_MCSI1TX        =       1,
    /** Synchronization event 1 (generic name) */
    CSL_DMA_SYNC_EVT1           =       1,
    /** Channel synchronized on MCSI_1 Receive (handler default) */
    CSL_DMA_SYNC_MCSI1RX        =       2,
    /** Synchronization event 2 (generic name) */
    CSL_DMA_SYNC_EVT2           =       2,
    /** Channel synchronized on MCSI_2 Transmit (handler default) */
    CSL_DMA_SYNC_MCSI2TX        =       3,
    /** Synchronization event 3 (generic name) */
    CSL_DMA_SYNC_EVT3           =       3,
    /** Channel synchronized on MCSI_2 Receive (handler default) */
    CSL_DMA_SYNC_MCSI2RX        =       4,
    /** Synchronization event 4 (generic name) */
    CSL_DMA_SYNC_EVT4           =       4,
    /** Channel synchronized on external DMA request zero (handler default) */
    CSL_DMA_SYNC_MPUIO2         =       5,
    /** Synchronization event 5 (generic name) */
    CSL_DMA_SYNC_EVT5           =       5,
    /** Channel synchronized on external DMA request one (handler default) */
    CSL_DMA_SYNC_MPUIO4         =       6,
    /** Synchronization event 6 (generic name) */
    CSL_DMA_SYNC_EVT6           =       6,
    /** Synchronization event 7 (generic name)*/
    CSL_DMA_SYNC_EVT7           =       7,
    /** Channel synchronized on McBSP1 Transmit (handler default) */
    CSL_DMA_SYNC_MCBSP1TX       =       8,
    /** Synchronization event 8 (generic name) */
    CSL_DMA_SYNC_EVT8           =       8,
    /** Channel synchronized on McBSP1 Receive (handler default) */
    CSL_DMA_SYNC_MCBSP1RX       =       9,
    /** Synchronization event 9 (generic name) */
    CSL_DMA_SYNC_EVT9           =       9,
    /** Channel synchronized on McBSP1 Transmit (handler default) */
    CSL_DMA_SYNC_MCBSP3TX       =       10,
    /** Synchronization event 10 (generic name) */
    CSL_DMA_SYNC_EVT10           =      10,
    /** Channel synchronized on McBSP1 Receive (handler default) */
    CSL_DMA_SYNC_MCBSP3RX       =       11,
    /** Synchronization event 11 (generic name) */
    CSL_DMA_SYNC_EVT11           =      11,
    /** Channel synchronized on UART1 Transmit (handler default) */
    CSL_DMA_SYNC_UART1TX        =       12,
    /** Synchronization event 12 (generic name) */
    CSL_DMA_SYNC_EVT12           =      12,
    /** Channel synchronized on UART1 Recieve (handler default) */
    CSL_DMA_SYNC_UART1RX        =       13,
    /** Synchronization event 13 (generic name) */
    CSL_DMA_SYNC_EVT13           =      13,
    /** Channel synchronized on UART2 Transmit (handler default) */
    CSL_DMA_SYNC_UART2TX        =       14,
    /** Synchronization event 14 (generic name) */
    CSL_DMA_SYNC_EVT14           =      14,
    /** Channel synchronized on UART2 Recieve (handler default) */
    CSL_DMA_SYNC_UART2RX        =       15,
    /** Synchronization event 15 (generic name) */
    CSL_DMA_SYNC_EVT15           =      15,
    /** Synchronization event 16 (generic name)*/
    CSL_DMA_SYNC_EVT16           =      16,
    /** Synchronization event 17 (generic name)*/
    CSL_DMA_SYNC_EVT17           =      17,
    /** Channel synchronized on UART3 Transmit (handler default) */
    CSL_DMA_SYNC_UART3TX        =       18,
    /** Synchronization event 18 (generic name) */
    CSL_DMA_SYNC_EVT18           =      18,
    /** Channel synchronized on UART3 Recieve (handler default) */
    CSL_DMA_SYNC_UART3RX        =       19,
    /** Synchronization event 19 (generic name) */
    CSL_DMA_SYNC_EVT19           =      19
} CSL_DmaSync;

/** @brief Enumerations for Frame Synchronization
 *
 * This enumeration is used to select the synchronization for transfer.
 */
typedef enum {
    /** Element synchronized transfer */
    CSL_DMA_FRAMESYNC_DISABLE   =             0,
    /** Frame synchronized transfer */
    CSL_DMA_FRAMESYNC_ENABLE    =             1
} CSL_DmaFrameSync;

/** @brief Enumerations for type having values ON and OFF
 *
 * This enumeration is used to select the state of certain parameters of
 * channel that have two states ON and OFF.
 */
typedef enum {
    /** On - Some property is to turned ON */
    CSL_DMA_ONOFF_OFF           =             0,
    /** Off - Some property is to turned OFF */
    CSL_DMA_ONOFF_ON            =             1
} CSL_DmaOnOff;

/** @brief Enumerations for DMA operations
 *
 * This enumeration is used to select the control command that has to be
 * passed to the CSL_dmaHwControl function.
 */
typedef enum {
    /** Start data transfer (argument type: NULL ) */
    CSL_DMA_CMD_START               =             0,
    /** Stop data transfer (argument type: NULL ) */
    CSL_DMA_CMD_STOP                =             1,
    /** Change source address (argument type: Uint32 * ) */
    CSL_DMA_CMD_CHNG_SRC            =             2,
    /** Change destination address (argument type: Uint32 * ) */
    CSL_DMA_CMD_CHNG_DST            =             3,
    /** Change element count (argument type: Uint16 * ) */
    CSL_DMA_CMD_CHNG_ELEMENT_COUNT  =             4,
    /** Change frame count (argument type: Uint16 * ) */
    CSL_DMA_CMD_CHNG_FRAME_COUNT    =             5,
    /** Clear Channel Status Register (argument type: NULL * ) */
    CSL_DMA_CMD_CLEAR_CHANNEL_STATUS =            6,
    /** Notify h/w the end of register programming (argument type: NULL * ) */
    CSL_DMA_CMD_NOTIFY_ENDPROG      =             7
} CSL_DmaHwControlCmd;

/** @brief Enumerations for index mode
 *
 * This enumeration is used to select the indexing mode to be same or
 * different for source and destination.
 */
typedef enum {
    /** Source and destination index modes are same */
    CSL_DMA_INDEXMODE_SAME          =             0,
    /** Source and destination index modes are different */
    CSL_DMA_INDEXMODE_DIFF          =             1
} CSL_DmaIndexMode;

/** @brief Enumerations for h/w status query
 *
 * This enumeration is used to select the hardware status query that has to be
 * passed to the CSL_dmaGetHwStatus function.
 */
typedef enum {
    /** Get status of DMA channel */
    CSL_DMA_QUERY_STATUS            =             0
} CSL_DmaHwStatusQuery;

/** @brief Enumerations for chip context query
 *
 * This enumeration is used to select the chip context query that has to be
 * passed to the CSL_dmaGetChipCtxt function.
 */
typedef enum {
    /** Get event ID for a DMA channel */
    CSL_DMA_CHIPCTXTQUERY_EVENTID       =             0
} CSL_DmaChipCtxtQuery;

/** Defines reset values of CSL_DmaHwSetupSrcPort structure members. */
#define CSL_DMA_DEFAULTS_SRCPORT  { \
    (CSL_DmaBurstEn)CSL_DMA_CSDP_SRCBEN_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CSDP_SRCPACK_RESETVAL, \
    (CSL_DmaPort)CSL_DMA_CSDP_SRC_RESETVAL, \
    (CSL_DmaAmode)CSL_DMA_CCR_SRCAMODE_RESETVAL, \
    ((((Uint32)CSL_DMA_CSSAU_CSSAU_RESETVAL >> 1) << 16) + (((Uint32)CSL_DMA_CSSAL_CSSAL_RESETVAL >> 1) & 0xffff)), \
    (Uint16)CSL_DMA_CSFI_CSFI_RESETVAL, \
    (Uint16)CSL_DMA_CSEI_CSEI_RESETVAL \
    }

/** Defines reset values of CSL_DmaHwSetupDstPort structure members. */
#define CSL_DMA_DEFAULTS_DSTPORT  { \
    (CSL_DmaBurstEn)CSL_DMA_CSDP_DSTBEN_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CSDP_DSTPACK_RESETVAL, \
    (CSL_DmaPort)CSL_DMA_CSDP_DST_RESETVAL, \
    (CSL_DmaAmode)CSL_DMA_CCR_DSTAMODE_RESETVAL, \
    ((((Uint32)CSL_DMA_CDSAU_CDSAU_RESETVAL >> 1) << 16) + (((Uint32)CSL_DMA_CDSAL_CDSAL_RESETVAL >> 1) & 0xffff)), \
    (Uint16)CSL_DMA_CDFI_CDFI_RESETVAL, \
    (Uint16)CSL_DMA_CDEI_CDEI_RESETVAL \
    }

/** Defines reset values of CSL_DmaHwSetupChannel structure members. */
#define CSL_DMA_DEFAULTS_CHANNEL  { \
    (CSL_DmaDataSize)CSL_DMA_CSDP_DATATYPE_RESETVAL, \
    (Uint16)CSL_DMA_CEN_CEN_RESETVAL, \
    (Uint16)CSL_DMA_CFN_CFN_RESETVAL, \
    (CSL_DmaPriority)CSL_DMA_CCR_PRIO_RESETVAL, \
    (CSL_DmaSync)CSL_DMA_CCR_SYNC_RESETVAL, \
    (CSL_DmaFrameSync)CSL_DMA_CCR_FS_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CCR_ENDPROG_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CCR_REPEAT_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CCR_AUTOINIT_RESETVAL \
    }

/** Defines reset values of CSL_DmaHwSetupIntr structure members. */
#define CSL_DMA_DEFAULTS_INTR  { \
    (CSL_DmaOnOff)CSL_DMA_CICR_BLOCKIE_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CICR_LASTIE_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CICR_FRAMEIE_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CICR_FIRSTHALFIE_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CICR_DROPIE_RESETVAL, \
    (CSL_DmaOnOff)CSL_DMA_CICR_TIMEOUTIE_RESETVAL \
    }
/** Defines reset values of CSL_DmaHwSetupGlobal structure members. */
#define CSL_DMA_DEFAULTS_GLOBAL  { \
    (CSL_DmaOnOff)CSL_DMA_GCR_AUTOGATINGON_RESETVAL, \
    (Bool)CSL_DMA_GCR_FREE_RESETVAL, \
    (Bool)CSL_DMA_GCR_APIEXCL_RESETVAL, \
    (CSL_DmaPriority)CSL_DMA_GCR_APIPRIO_RESETVAL, \