cslr_clkrst.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 228 行

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228 行
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#ifndef _CSLR_CLKRST_001_H_#define _CSLR_CLKRST_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    volatile Uint16 DSP_CKCTL;    const char RSVD0[1];    volatile Uint16 DSP_IDLECT1;    const char RSVD1[1];    volatile Uint16 DSP_IDLECT2;    const char RSVD2[1];    volatile Uint16 DSP_EWUPCT;    const char RSVD3[1];    volatile Uint16 DSP_RSTCT1;    const char RSVD4[1];    volatile Uint16 DSP_RSTCT2;    const char RSVD5[1];    volatile Uint16 DSP_SYSST;    const char RSVD6[1];    volatile Uint16 DSP_CKOUT1;    const char RSVD7[1];    volatile Uint16 DSP_CKOUT2;} CSL_ClkrstRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile ioport CSL_ClkrstRegs  * CSL_ClkrstRegsOvly;/**************************************************************************\* Register Id's\**************************************************************************/typedef enum  {   CSL_CLKRST_DSP_CKCTL = 0x0000u,   CSL_CLKRST_DSP_IDLECT1 = 0x0002u,   CSL_CLKRST_DSP_IDLECT2 = 0x0004u,   CSL_CLKRST_DSP_EWUPCT = 0x0006u,   CSL_CLKRST_DSP_RSTCT1 = 0x0008u,   CSL_CLKRST_DSP_RSTCT2 = 0x000au,   CSL_CLKRST_DSP_SYSST = 0x000cu,   CSL_CLKRST_DSP_CKOUT1 = 0x000eu,   CSL_CLKRST_DSP_CKOUT2 = 0x0010u} CSL_ClkrstRegIds;/**************************************************************************\* Field Definition Macros\**************************************************************************//* DSP_CKCTL */#define CSL_CLKRST_DSP_CKCTL_TIMXO_MASK  (0x00000100u)#define CSL_CLKRST_DSP_CKCTL_TIMXO_SHIFT (0x00000008u)#define CSL_CLKRST_DSP_CKCTL_TIMXO_RESETVAL (0x00000001u)#define CSL_CLKRST_DSP_CKCTL_TIMXO_IP_REF_CK (0x00000000u)#define CSL_CLKRST_DSP_CKCTL_TIMXO_CK_GEN2 (0x00000001u)#define CSL_CLKRST_DSP_CKCTL_PERDIV_MASK (0x00000003u)#define CSL_CLKRST_DSP_CKCTL_PERDIV_SHIFT (0x00000000u)#define CSL_CLKRST_DSP_CKCTL_PERDIV_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_CKCTL_RESETVAL    (0x00000100u)/* DSP_IDLECT1 */#define CSL_CLKRST_DSP_IDLECT1_IDLTIM_DSP_MASK (0x00000100u)#define CSL_CLKRST_DSP_IDLECT1_IDLTIM_DSP_SHIFT (0x00000008u)#define CSL_CLKRST_DSP_IDLECT1_IDLTIM_DSP_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLTIM_DSP_IDLE_ACTIVE (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLTIM_DSP_IDLE_STOP (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_WKUP_MODE_MASK (0x00000040u)#define CSL_CLKRST_DSP_IDLECT1_WKUP_MODE_SHIFT (0x00000006u)#define CSL_CLKRST_DSP_IDLECT1_WKUP_MODE_RESETVAL (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_IDLDPLL_DSP_MASK (0x00000020u)#define CSL_CLKRST_DSP_IDLECT1_IDLDPLL_DSP_SHIFT (0x00000005u)#define CSL_CLKRST_DSP_IDLECT1_IDLDPLL_DSP_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLIF_DSP_MASK (0x00000010u)#define CSL_CLKRST_DSP_IDLECT1_IDLIF_DSP_SHIFT (0x00000004u)#define CSL_CLKRST_DSP_IDLECT1_IDLIF_DSP_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLPER_DSP_MASK (0x00000004u)#define CSL_CLKRST_DSP_IDLECT1_IDLPER_DSP_SHIFT (0x00000002u)#define CSL_CLKRST_DSP_IDLECT1_IDLPER_DSP_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLPER_DSP_IDLE_ACTIVE (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLPER_DSP_IDLE_STOP (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_IDLXORP_DSP_MASK (0x00000002u)#define CSL_CLKRST_DSP_IDLECT1_IDLXORP_DSP_SHIFT (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_IDLXORP_DSP_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLXORP_DSP_IDLE_ACTIVE (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLXORP_DSP_IDLE_STOP (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_IDLWDT_DSP_MASK (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_IDLWDT_DSP_SHIFT (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLWDT_DSP_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLWDT_DSP_IDLE_ACTIVE (0x00000000u)#define CSL_CLKRST_DSP_IDLECT1_IDLWDT_DSP_IDLE_STOP (0x00000001u)#define CSL_CLKRST_DSP_IDLECT1_RESETVAL  (0x00000040u)/* DSP_IDLECT2 */#define CSL_CLKRST_DSP_IDLECT2_EN_TIMCK_MASK (0x00000020u)#define CSL_CLKRST_DSP_IDLECT2_EN_TIMCK_SHIFT (0x00000005u)#define CSL_CLKRST_DSP_IDLECT2_EN_TIMCK_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_TIMCK_STOPPED (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_TIMCK_ACTIVE (0x00000001u)#define CSL_CLKRST_DSP_IDLECT2_EN_PERCK_MASK (0x00000004u)#define CSL_CLKRST_DSP_IDLECT2_EN_PERCK_SHIFT (0x00000002u)#define CSL_CLKRST_DSP_IDLECT2_EN_PERCK_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_PERCK_STOPPED (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_PERCK_ACTIVE (0x00000001u)#define CSL_CLKRST_DSP_IDLECT2_EN_XORPCK_MASK (0x00000002u)#define CSL_CLKRST_DSP_IDLECT2_EN_XORPCK_SHIFT (0x00000001u)#define CSL_CLKRST_DSP_IDLECT2_EN_XORPCK_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_XORPCK_STOPPED (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_XORPCK_ACTIVE (0x00000001u)#define CSL_CLKRST_DSP_IDLECT2_EN_WDTCK_MASK (0x00000001u)#define CSL_CLKRST_DSP_IDLECT2_EN_WDTCK_SHIFT (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_WDTCK_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_WDTCK_STOPPED (0x00000000u)#define CSL_CLKRST_DSP_IDLECT2_EN_WDTCK_ACTIVE (0x00000001u)#define CSL_CLKRST_DSP_IDLECT2_RESETVAL  (0x00000000u)/* DSP_EWUPCT */#define CSL_CLKRST_DSP_EWUPCT_RESETVAL   (0x00000000u)/* DSP_RSTCT1 */#define CSL_CLKRST_DSP_RSTCT1_RESETVAL   (0x00000000u)/* DSP_RSTCT2 */#define CSL_CLKRST_DSP_RSTCT2_WD_PER_EN_MASK (0x00000002u)#define CSL_CLKRST_DSP_RSTCT2_WD_PER_EN_SHIFT (0x00000001u)#define CSL_CLKRST_DSP_RSTCT2_WD_PER_EN_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_RSTCT2_WD_PER_EN_RESET (0x00000000u)#define CSL_CLKRST_DSP_RSTCT2_WD_PER_EN_ENABLED (0x00000001u)#define CSL_CLKRST_DSP_RSTCT2_PER_EN_MASK (0x00000001u)#define CSL_CLKRST_DSP_RSTCT2_PER_EN_SHIFT (0x00000000u)#define CSL_CLKRST_DSP_RSTCT2_PER_EN_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_RSTCT2_PER_EN_RESET (0x00000000u)#define CSL_CLKRST_DSP_RSTCT2_PER_EN_ENABLED (0x00000001u)#define CSL_CLKRST_DSP_RSTCT2_RESETVAL   (0x00000000u)/* DSP_SYSST */#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_MASK (0x00003800u)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_SHIFT (0x0000000Bu)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_FULL_SYNC (0x00000000u)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_SYNC_SCAL (0x00000002u)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_BYPASS (0x00000005u)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_MM3 (0x00000006u)#define CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_MM4 (0x00000007u)#define CSL_CLKRST_DSP_SYSST_IDLE_ARM_MASK (0x00000040u)#define CSL_CLKRST_DSP_SYSST_IDLE_ARM_SHIFT (0x00000006u)#define CSL_CLKRST_DSP_SYSST_IDLE_ARM_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_SYSST_IDLE_ARM_ACTIVE (0x00000000u)#define CSL_CLKRST_DSP_SYSST_IDLE_ARM_IDLE (0x00000001u)#define CSL_CLKRST_DSP_SYSST_POR_MASK    (0x00000020u)#define CSL_CLKRST_DSP_SYSST_POR_SHIFT   (0x00000005u)#define CSL_CLKRST_DSP_SYSST_POR_RESETVAL (0x00000001u)#define CSL_CLKRST_DSP_SYSST_POR_NO      (0x00000000u)#define CSL_CLKRST_DSP_SYSST_POR_YES     (0x00000001u)#define CSL_CLKRST_DSP_SYSST_EXT_RST_MASK (0x00000010u)#define CSL_CLKRST_DSP_SYSST_EXT_RST_SHIFT (0x00000004u)#define CSL_CLKRST_DSP_SYSST_EXT_RST_RESETVAL (0x00000001u)#define CSL_CLKRST_DSP_SYSST_EXT_RST_NO  (0x00000000u)#define CSL_CLKRST_DSP_SYSST_EXT_RST_YES (0x00000001u)#define CSL_CLKRST_DSP_SYSST_DSP_ARM_RST_MASK (0x00000008u)#define CSL_CLKRST_DSP_SYSST_DSP_ARM_RST_SHIFT (0x00000003u)#define CSL_CLKRST_DSP_SYSST_DSP_ARM_RST_RESETVAL (0x00000001u)#define CSL_CLKRST_DSP_SYSST_DSP_ARM_RST_ENABLE_MPU (0x00000000u)#define CSL_CLKRST_DSP_SYSST_DSP_ARM_RST_RESET_MPU (0x00000001u)#define CSL_CLKRST_DSP_SYSST_ARM_WDRST_MASK (0x00000004u)#define CSL_CLKRST_DSP_SYSST_ARM_WDRST_SHIFT (0x00000002u)#define CSL_CLKRST_DSP_SYSST_ARM_WDRST_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_SYSST_ARM_WDRST_NO (0x00000000u)#define CSL_CLKRST_DSP_SYSST_ARM_WDRST_YES (0x00000001u)#define CSL_CLKRST_DSP_SYSST_GLOB_SWRST_MASK (0x00000002u)#define CSL_CLKRST_DSP_SYSST_GLOB_SWRST_SHIFT (0x00000001u)#define CSL_CLKRST_DSP_SYSST_GLOB_SWRST_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_SYSST_GLOB_SWRST_NO (0x00000000u)#define CSL_CLKRST_DSP_SYSST_GLOB_SWRST_YES (0x00000001u)#define CSL_CLKRST_DSP_SYSST_DSP_WDRST_MASK (0x00000001u)#define CSL_CLKRST_DSP_SYSST_DSP_WDRST_SHIFT (0x00000000u)#define CSL_CLKRST_DSP_SYSST_DSP_WDRST_RESETVAL (0x00000000u)#define CSL_CLKRST_DSP_SYSST_DSP_WDRST_NO (0x00000000u)#define CSL_CLKRST_DSP_SYSST_DSP_WDRST_YES (0x00000001u)#define CSL_CLKRST_DSP_SYSST_RESETVAL    (0x00000038u)/* DSP_CKOUT1 */#define CSL_CLKRST_DSP_CKOUT1_RESETVAL   (0x00000000u)/* DSP_CKOUT2 */#define CSL_CLKRST_DSP_CKOUT2_RESETVAL   (0x00000000u)#endif

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