soc.h

dsp在音频处理中的运用

/** @brief Peripheral Instance of DMA */
#define     CSL_EMIF    (0)

/** @brief Peripheral Instance of SSW */
#define     CSL_SSW     (0)  /** Instance of SSW */

/** @brief Peripheral Instances of SPDIF*/
#define     CSL_SPDIF            (0)  /** Instance 1 of SPDIF */

/** @brief Peripheral Instance of DMA */
#define     CSL_DMA     (0)  /** Instance of DMA */

/** @brief Peripheral Instances of SPI*/
#define     CSL_MIBSPI_1    (0)  /** Instance 1 of MIBSPI */

#define     CSL_MIBSPI_3    (2)  /** Instance 3 of MIBSPI */


/** @brief Peripheral Instances of IRDA */
/** This is part of Instance 1 of UART. */
#define     CSL_IRDA_1     (0)  /** Instance 1 of IRDA */

/** This is part of Instance 3 of UART. There is no Instance 2 of IRDA,
    as Instance 2 of UART doesn't support IRDA
 */
#define     CSL_IRDA_3      (1)  /** Instance 3 of IRDA */

/** @brief Peripheral Instances of MCBSP*/
#define     CSL_MCBSP_1     (0)  /** Instance 1 of McBSP */

#define     CSL_MCBSP_2     (1)  /** Instance 2 of McBSP */

#define     CSL_MCBSP_3     (2)  /** Instance 3 of McBSP */

/** @brief Peripheral Instance of I2C */
#define     CSL_I2C_1       (0)  /** Instance 1 of I2C */

/** @brief Peripheral Instance of MMCSD */
#define     CSL_MMCSD_2     (0)  /** Instance 1 of MMCSD */

/** @brief Peripheral Instances of TIMER */
#define     CSL_TIMER_1     (0)  /** Instance 1 of TIMER */

#define     CSL_TIMER_2     (1)  /** Instance 2 of TIMER */

#define     CSL_TIMER_3     (2)  /** Instance 3 of TIMER */

/** @brief Peripheral Instance of CLKRST */

#define     CSL_ICACHE      (0)

/** @brief Peripheral Instance of CLKRST */
#define     CSL_CLKRST      (0)   /** Instance 1 of CLKRST */

/** @brief Peripheral Instances of Mailbox */
#define     CSL_MBX_DSP2ARM1     (0) /** Instance 1 of DSP to ARM Mailbox */

#define     CSL_MBX_DSP2ARM2     (1) /** Instance 2 of DSP to ARM Mailbox */

#define     CSL_MBX_ARM2DSP1     (2) /** Instance 1 of ARM to DSP Mailbox */

#define     CSL_MBX_ARM2DSP2     (3) /** Instance 2 of ARM to DSP Mailbox */

/** @brief Peripheral Instances of MCASP*/
#define    CSL_MCASP_1          (0)  /** Instance 1 of McASP */

#define    CSL_MCASP_2          (1)  /** Instance 2 of McASP */

/** @brief Peripheral Instance of WDTimer  */
#define CSL_WDT            (0)  /** Instance1 of WDTimer  */

/** @brief Peripheral Instances of GPTIMER  */
#define CSL_GPTIMER_1      (0)  /** Instance1 of GPTimer  */

#define CSL_GPTIMER_2      (1)  /** Instance2 of GPTimer  */

#define CSL_GPTIMER_3      (2)  /** Instance3 of GPTimer  */

#define CSL_GPTIMER_4      (3)  /** Instance4 of GPTimer  */

#define CSL_GPTIMER_5      (4)  /** Instance5 of GPTimer  */

#define CSL_GPTIMER_6      (5)  /** Instance6 of GPTimer  */

#define CSL_GPTIMER_7      (6)  /** Instance7 of GPTimer  */

#define CSL_GPTIMER_8      (7)  /** Instance8 of GPTimer  */

/** @brief Peripheral Instance of ADCC  */
#define CSL_ADCC           (0)  /** Instance of ADCC  */

/** @brief Peripheral Instance enumeration for GPIO  */
#define CSL_GPIO_1          (0)  /** Instance1 of GPIO  */

#define CSL_GPIO_2          (1)  /** Instance2 of GPIO  */

#define CSL_GPIO_3          (2)  /** Instance3 of GPIO  */

#define CSL_GPIO_4          (3)  /** Instance4 of GPIO  */

/** @brief Peripheral Instance enumeration for MCSI */
#define CSL_MCSI_1      (0) /** Instance1 of MCSI */

#define CSL_MCSI_2      (1) /** Instance2 of MCSI */

/** @brief Peripheral Instances of SPI*/
#define CSL_SPI         (0)
                                                     
/* Interrupt Event Counts */
#define __CSL_INTC_EVENTID__IVPDCNT_          (16)
#define __CSL_INTC_EVENTID__IVPHCNT_          (16)
#define __CSL_INTC_EVENTID__INTC20CNT_        (16)
#define __CSL_INTC_EVENTID__INTC21CNT_        (64)


#define _CSL_INTC_EVENTID__IVPDSTART        (0)

#define CSL_INTC_EVENTID_RESET              (_CSL_INTC_EVENTID__IVPDSTART + 0)      /**< Reset */
#define CSL_INTC_EVENTID_SINT1              (_CSL_INTC_EVENTID__IVPDSTART + 1)      /**< Software Interrupt #1 */
#define CSL_INTC_EVENTID_EMUTEST            (_CSL_INTC_EVENTID__IVPDSTART + 2)      /**< Emulator/test interrupt */
#define CSL_INTC_EVENTID_L20INTHFIQ         (_CSL_INTC_EVENTID__IVPDSTART + 3)      /**< Level 2.0 interrupt handler */
#define CSL_INTC_EVENTID_TCABORT            (_CSL_INTC_EVENTID__IVPDSTART + 4)      /**< TC_ABORT interrupt */
#define CSL_INTC_EVENTID_MBX1               (_CSL_INTC_EVENTID__IVPDSTART + 5)      /**< Mailbox 1 */
#define CSL_INTC_EVENTID_L21INTHFIQ         (_CSL_INTC_EVENTID__IVPDSTART + 6)      /**< Level 2.1 interrupt handler */
#define CSL_INTC_EVENTID_IRQ2GPIO1          (_CSL_INTC_EVENTID__IVPDSTART + 7)      /**< IRQ2 GPIO1 */
#define CSL_INTC_EVENTID_TIMER3             (_CSL_INTC_EVENTID__IVPDSTART + 8)      /**< DSP Timer3 */
#define CSL_INTC_EVENTID_DMACH1             (_CSL_INTC_EVENTID__IVPDSTART + 9)      /**< DMA Channel 1 */
#define CSL_INTC_EVENTID_MPUIINT            (_CSL_INTC_EVENTID__IVPDSTART + 10)     /**< MPUI */
#define CSL_INTC_EVENTID_SINT11             (_CSL_INTC_EVENTID__IVPDSTART + 11)     /**< Reserved */
#define CSL_INTC_EVENTID_UART3              (_CSL_INTC_EVENTID__IVPDSTART + 12)     /**< UART3 */
#define CSL_INTC_EVENTID_WDTIM              (_CSL_INTC_EVENTID__IVPDSTART + 13)     /**< Watchdog */
#define CSL_INTC_EVENTID_DMACH4             (_CSL_INTC_EVENTID__IVPDSTART + 14)     /**< DMA Channel 4 */
#define CSL_INTC_EVENTID_DMACH5             (_CSL_INTC_EVENTID__IVPDSTART + 15)     /**< DMA Channel 5 */

#define _CSL_INTC_EVENTID__IVPDEND          (_CSL_INTC_EVENTID__IVPDSTART + __CSL_INTC_EVENTID__IVPDCNT_ - 1)

#define _CSL_INTC_EVENTID__IVPHSTART        (_CSL_INTC_EVENTID__IVPDEND + 1)

#define CSL_INTC_EVENTID_STIO               (_CSL_INTC_EVENTID__IVPHSTART + 0)      /**< STIO */
#define CSL_INTC_EVENTID_L21INTHIRQ         (_CSL_INTC_EVENTID__IVPHSTART + 1)      /**< Level 2.1 IRQ */
#define CSL_INTC_EVENTID_DMACH0             (_CSL_INTC_EVENTID__IVPHSTART + 2)      /**< DMA Channel 0 */
#define CSL_INTC_EVENTID_MBX2               (_CSL_INTC_EVENTID__IVPHSTART + 3)      /**< Mailbox 2 */
#define CSL_INTC_EVENTID_DMACH2             (_CSL_INTC_EVENTID__IVPHSTART + 4)      /**< DMA Channel 2 */
#define CSL_INTC_EVENTID_DMACH3             (_CSL_INTC_EVENTID__IVPHSTART + 5)      /**< DMA Channel 3 */
#define CSL_INTC_EVENTID_TIMER2             (_CSL_INTC_EVENTID__IVPHSTART + 6)      /**< DSP Timer 2 */
#define CSL_INTC_EVENTID_TIMER1             (_CSL_INTC_EVENTID__IVPHSTART + 7)      /**< DSP Timer 1 */
#define CSL_INTC_EVENTID_BERR               (_CSL_INTC_EVENTID__IVPHSTART + 8)      /**< Bus Error */
#define CSL_INTC_EVENTID_DLOG               (_CSL_INTC_EVENTID__IVPHSTART + 9)      /**< Emulator interrupt DLOG */
#define CSL_INTC_EVENTID_RTOS               (_CSL_INTC_EVENTID__IVPHSTART + 10)     /**< Emulator interrupt RTOS */
#define CSL_INTC_EVENTID_SINT27             (_CSL_INTC_EVENTID__IVPHSTART + 11)     /**< Software Interrupt #27 */
#define CSL_INTC_EVENTID_SINT28             (_CSL_INTC_EVENTID__IVPHSTART + 12)     /**< Software Interrupt #28 */
#define CSL_INTC_EVENTID_SINT29             (_CSL_INTC_EVENTID__IVPHSTART + 13)     /**< Software Interrupt #29 */
#define CSL_INTC_EVENTID_SINT30             (_CSL_INTC_EVENTID__IVPHSTART + 14)     /**< Software Interrupt #30 */
#define CSL_INTC_EVENTID_SINT31             (_CSL_INTC_EVENTID__IVPHSTART + 15)     /**< Software Interrupt #31 */

#define _CSL_INTC_EVENTID__IVPHEND          (_CSL_INTC_EVENTID__IVPHSTART + __CSL_INTC_EVENTID__IVPHCNT_ - 1)

#define _CSL_INTC_EVENTID__INTC20START      (_CSL_INTC_EVENTID__IVPHEND + 1)

#define CSL_INTC_EVENTID_MCBSP3_TX          (_CSL_INTC_EVENTID__INTC20START + 0)    /**< McBSP3 TX */
#define CSL_INTC_EVENTID_MCBSP3_RX          (_CSL_INTC_EVENTID__INTC20START + 1)    /**< McBSP3 RX */
#define CSL_INTC_EVENTID_MCBSP1_TX          (_CSL_INTC_EVENTID__INTC20START + 2)    /**< McBSP1 TX */
#define CSL_INTC_EVENTID_MCBSP1_RX          (_CSL_INTC_EVENTID__INTC20START + 3)    /**< McBSP1 RX */
#define CSL_INTC_EVENTID_UART2              (_CSL_INTC_EVENTID__INTC20START + 4)    /**< UART2 */
#define CSL_INTC_EVENTID_UART1              (_CSL_INTC_EVENTID__INTC20START + 5)    /**< UART1 */
#define CSL_INTC_EVENTID_MCSI1TX            (_CSL_INTC_EVENTID__INTC20START + 6)    /**< MCSI1 TX */
#define CSL_INTC_EVENTID_MCSI1RX            (_CSL_INTC_EVENTID__INTC20START + 7)    /**< MCSI1 RX */
#define CSL_INTC_EVENTID_MCSI2TX            (_CSL_INTC_EVENTID__INTC20START + 8)    /**< MCSI2 TX */
#define CSL_INTC_EVENTID_MCSI2RX            (_CSL_INTC_EVENTID__INTC20START + 9)    /**< MCSI2 RX */
#define CSL_INTC_EVENTID_MCSI1FERR          (_CSL_INTC_EVENTID__INTC20START + 10)   /**< MCSI1 Frame Error */
#define CSL_INTC_EVENTID_MCSI2FERR          (_CSL_INTC_EVENTID__INTC20START + 11)   /**< MCSI2 Frame Error */
#define CSL_INTC_EVENTID_IRQ2GPIO2          (_CSL_INTC_EVENTID__INTC20START + 12)   /**< IRQ2_GPIO2 */
#define CSL_INTC_EVENTID_IRQ2GPIO3          (_CSL_INTC_EVENTID__INTC20START + 13)   /**< IRQ2_GPIO3 */
#define CSL_INTC_EVENTID_IRQ2GPIO4          (_CSL_INTC_EVENTID__INTC20START + 14)   /**< IRQ2_GPIO4 */
#define CSL_INTC_EVENTID_I2C                (_CSL_INTC_EVENTID__INTC20START + 15)   /**< I2C */

#define _CSL_INTC_EVENTID__INTC20END        (_CSL_INTC_EVENTID__INTC20START + __CSL_INTC_EVENTID__INTC20CNT_ - 1)

#define _CSL_INTC_EVENTID__INTC21START      (_CSL_INTC_EVENTID__INTC20END + 1)


#define CSL_INTC_EVENTID_NFC                (_CSL_INTC_EVENTID__INTC21START + 0)    /**< NAND Flash */
#define CSL_INTC_EVENTID_GPTIMER1           (_CSL_INTC_EVENTID__INTC21START + 1)    /**< GPTIMER1 */
#define CSL_INTC_EVENTID_GPTIMER2           (_CSL_INTC_EVENTID__INTC21START + 2)    /**< GPTIMER2 */
#define CSL_INTC_EVENTID_GPTIMER3           (_CSL_INTC_EVENTID__INTC21START + 3)    /**< GPTIMER3 */
#define CSL_INTC_EVENTID_GPTIMER4           (_CSL_INTC_EVENTID__INTC21START + 4)    /**< GPTIMER4 */
#define CSL_INTC_EVENTID_GPTIMER5           (_CSL_INTC_EVENTID__INTC21START + 5)    /**< GPTIMER5 */
#define CSL_INTC_EVENTID_GPTIMER6           (_CSL_INTC_EVENTID__INTC21START + 6)    /**< GPTIMER6 */
#define CSL_INTC_EVENTID_GPTIMER7           (_CSL_INTC_EVENTID__INTC21START + 7)    /**< GPTIMER7 */
#define CSL_INTC_EVENTID_GPTIMER8           (_CSL_INTC_EVENTID__INTC21START + 8)    /**< GPTIMER8 */
#define CSL_INTC_EVENTID_STIGIE             (_CSL_INTC_EVENTID__INTC21START + 9)    /**< STI global */
#define CSL_INTC_EVENTID_MCBSP2TX           (_CSL_INTC_EVENTID__INTC21START + 10)   /**< McBSP2 TX */
#define CSL_INTC_EVENTID_MCBSP2RX           (_CSL_INTC_EVENTID__INTC21START + 11)   /**< McBSP2 RX */
#define CSL_INTC_EVENTID_MCSI1RSTINT        (_CSL_INTC_EVENTID__INTC21START + 12)   /**< MCSI1_RST_INT */
#define CSL_INTC_EVENTID_MCSI2RSTINT        (_CSL_INTC_EVENTID__INTC21START + 13)   /**< MCSI2_RST_INT */
#define CSL_INTC_EVENTID_MMCSDIO2           (_CSL_INTC_EVENTID__INTC21START + 14)   /**< MMC/SDIO2 */
#define CSL_INTC_EVENTID_SPI                (_CSL_INTC_EVENTID__INTC21START + 15)   /**< SPI */
#define CSL_INTC_EVENTID_SSTCH1FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 16)   /**< SST FIFO empty (channel 1) */
#define CSL_INTC_EVENTID_SSTCH1FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 17)   /**< SST FIFO full (channel 1) */
#define CSL_INTC_EVENTID_SSRCH1OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 18)   /**< SSR overrun (channel 1) */
#define CSL_INTC_EVENTID_SSTCH2FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 19)   /**< SST FIFO empty (channel 2) */
#define CSL_INTC_EVENTID_SSTCH2FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 20)   /**< SST FIFO full (channel 2) */
#define CSL_INTC_EVENTID_SSRCH2OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 21)   /**< SSR overrun (channel 2) */
#define CSL_INTC_EVENTID_SSTCH3FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 22)   /**< SST FIFO empty (channel 3) */
#define CSL_INTC_EVENTID_SSTCH3FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 23)   /**< SST FIFO full (channel 3) */
#define CSL_INTC_EVENTID_SSRCH3OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 24)   /**< SSR overrun (channel 3) */
#define CSL_INTC_EVENTID_SSTCH4FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 25)   /**< SST FIFO empty (channel 4) */
#define CSL_INTC_EVENTID_SSTCH4FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 26)   /**< SST FIFO full (channel 4) */
#define CSL_INTC_EVENTID_SSRCH4OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 27)   /**< SSR overrun (channel 4) */
#define CSL_INTC_EVENTID_SSTCH5FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 28)   /**< SST FIFO empty (channel 5) */
#define CSL_INTC_EVENTID_SSTCH5FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 29)   /**< SST FIFO full (channel 5) */
#define CSL_INTC_EVENTID_SSRCH5OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 30)   /**< SSR overrun (channel 5) */
#define CSL_INTC_EVENTID_SSTCH6FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 31)   /**< SST FIFO empty (channel 6) */
#define CSL_INTC_EVENTID_SSTCH6FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 32)   /**< SST FIFO full (channel 6) */
#define CSL_INTC_EVENTID_SSRCH6OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 33)   /**< SSR overrun (channel 6) */
#define CSL_INTC_EVENTID_SSTCH7FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 34)   /**< SST FIFO empty (channel 7) */
#define CSL_INTC_EVENTID_SSTCH7FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 35)   /**< SST FIFO full (channel 7) */
#define CSL_INTC_EVENTID_SSRCH7OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 36)   /**< SSR overrun (channel 7) */
#define CSL_INTC_EVENTID_SSTCH0FIFOEMPTY    (_CSL_INTC_EVENTID__INTC21START + 37)   /**< SST FIFO empty (channel 0) */
#define CSL_INTC_EVENTID_SSTCH0FIFOFULL     (_CSL_INTC_EVENTID__INTC21START + 38)   /**< SST FIFO full (channel 0) */
#define CSL_INTC_EVENTID_SSRCH0OVERRUN      (_CSL_INTC_EVENTID__INTC21START + 39)   /**< SSR overrun (channel 0) */
#define CSL_INTC_EVENTID_GDDLCH0            (_CSL_INTC_EVENTID__INTC21START + 40)   /**< GDD_LCH0 */
#define CSL_INTC_EVENTID_GDDLCH1            (_CSL_INTC_EVENTID__INTC21START + 41)   /**< GDD_LCH1 */
#define CSL_INTC_EVENTID_GDDLCH2            (_CSL_INTC_EVENTID__INTC21START + 42)   /**< GDD_LCH2 */
#define CSL_INTC_EVENTID_GDDLCH3            (_CSL_INTC_EVENTID__INTC21START + 43)   /**< GDD_LCH3 */
#define CSL_INTC_EVENTID_GDDLCH4            (_CSL_INTC_EVENTID__INTC21START + 44)   /**< GDD_LCH4 */
#define CSL_INTC_EVENTID_GDDLCH5            (_CSL_INTC_EVENTID__INTC21START + 45)   /**< GDD_LCH5 */
#define CSL_INTC_EVENTID_GDDLCH6            (_CSL_INTC_EVENTID__INTC21START + 46)   /**< GDD_LCH6 */
#define CSL_INTC_EVENTID_GDDLCH7            (_CSL_INTC_EVENTID__INTC21START + 47)   /**< GDD_LCH7 */

#define _CSL_INTC_EVENTID__INTC21END        (_CSL_INTC_EVENTID__INTC21START + __CSL_INTC_EVENTID__INTC21CNT_ - 1)


#endif  /* _SOC_H_ */