soc.h

dsp在音频处理中的运用

#ifndef _SOC_H_
#define _SOC_H_

/**************************************************************************\
* 5912 C55 soc file
\**************************************************************************/

#include <cslr.h>

/**************************************************************************\
* Peripheral Instance count
\**************************************************************************/
/** @brief Number of UART instances */
#define CSL_UART_CNT                3

/** @brief Number of Static Switch(SSW) instances */
#define CSL_SSW_CNT                 1

/** @brief Number of SPI instances */
#define CSL_MIBSPI_CNT              2

/** @brief Number of SPDIF instances */
#define CSL_SPDIF_CNT               1

/** @brief Number of EMIF instances */
#define CSL_EMIF_CNT                1

/** @brief Number of DMA instances */
#define CSL_DMA_CNT                 1

/** @brief Number of IRDA instances */
#define CSL_IRDA_CNT                2

/** @brief Number of MCBSP instances */
#define CSL_MCBSP_CNT               3

/** @brief Number of I2C instances */
#define CSL_I2C_CNT                 1

/** @brief Number of MMCSD instances */
#define CSL_MMCSD_CNT               1

/** @brief Number of TIMER instances */
#define CSL_TIMER_CNT               3

/** @brief Number of INTC20 instances */
#define CSL_INTC20_CNT              1

/** @brief Number of McAsp instances */
#define CSL_MCASP_CNT               2

/** @brief Number of INTC21 instances */
#define CSL_INTC21_CNT              1

/** @brief Number of CLKRST instances */
#define CSL_CLKRST_CNT              1

/** @brief Number of MBX instances */
#define CSL_MBX_CNT                 4

/** @brief Number of GPTIMER instances */
#define CSL_GPTIMER_CNT             8

/** @brief Number of WDT instances */
#define CSL_WDT_CNT                 1

/** @brief Number of ADCC instances */
#define CSL_ADCC_CNT                1

/** @brief Number of GPIO instances */
#define CSL_GPIO_CNT                4

/** @brief Number of MCSI instances */
#define CSL_MCSI_CNT                2

/** @brief Number of ICACHE instances */
#define CSL_ICACHE_CNT              1

/** @brief Number of SPI instances */
#define CSL_SPI_CNT                 1

/**************************************************************************\
* Peripheral Base Address
\**************************************************************************/
/** @brief Base address of CHIP peripheral registers */
#define CSL_CHIP_REGS               ( 0x00000000u)

/** @brief Base address of EMIF peripheral registers */
#define CSL_EMIF_1_REGS             (0x00000800u)

/** @brief Base address of UART1 peripheral registers */
#define CSL_UART_1_REGS             ( 0x00008000u)

/** @brief Base address of UART2 peripheral registers */
#define CSL_UART_2_REGS             ( 0x00008400u)

/** @brief Base address of UART3 peripheral registers */
#define CSL_UART_3_REGS             ( 0x0000CC00u)

/** @brief Base address of IRDA1 peripheral registers */
#define CSL_IRDA_1_REGS             ( CSL_UART_1_REGS)

/** @brief Base address of IRDA3 peripheral registers */
#define CSL_IRDA_3_REGS             ( CSL_UART_3_REGS)

/** @brief Base address of Stati Switch(SSW) peripheral registers */
#define CSL_SSW_1_REGS              ( 0x0000E400u)

/** @brief Base address of DMA peripheral registers */
#define CSL_DMA_1_REGS              ( 0x00000C00u)

/** @brief Base address of MIBSPI1 peripheral registers */
#define CSL_MIBSPI_1_REGS           (0x0000B000u)

/** @brief Base address of MIBSPI3 peripheral registers */
#define CSL_MIBSPI_3_REGS           (0x0000B400u)

/** @brief Base address of SPDIF peripheral registers */
#define CSL_SPDIF_1_REGS            (0x0000C000u)

/** @brief Base address of MCBSP1 peripheral registers */
#define CSL_MCBSP_1_REGS            ( 0x00008C00u)

/** @brief Base address of MCBSP2 peripheral registers */
#define CSL_MCBSP_2_REGS            ( 0x00008800u)

/** @brief Base address of MCBSP3 peripheral registers */
#define CSL_MCBSP_3_REGS            ( 0x0000B800u)

/** @brief Base address of I2C1 peripheral registers */
#define CSL_I2C_1_REGS              ( 0x00009C00u)

/** @brief Base address of MMCSD peripheral registers */
#define CSL_MMCSD_2_REGS            ( 0x0000BE00u)

/** @brief Base address of ICACHE peripheral registers */
#define CSL_ICACHE_REGS             ( 0x00001400u)

/** @brief Base address of TIMER1 peripheral registers */
#define CSL_TIMER_1_REGS            ( 0x00002800u)

/** @brief Base address of TIMER2 peripheral registers */
#define CSL_TIMER_2_REGS            ( 0x00002C00u)

/** @brief Base address of TIMER3 peripheral registers */
#define CSL_TIMER_3_REGS            ( 0x00003000u)

/** @brief Base address of INTC level2.0 peripheral registers */
#define CSL_INTC20_0_REGS           ( 0x00004800u)

/** @brief Base address of INTC level2.1 peripheral registers */
#define CSL_INTC21_0_REGS           ( 0x00004C00u)

/** @brief Base address of CLKRST peripheral registers */
#define CSL_CLKRST_1_REGS           (0x00004000u)

/** @brief Base address of MCASP peripheral registers */
#define CSL_MCASP_1_REGS            (0x0000B800u)

#define CSL_MCASP_2_REGS            (0x0000BC00u)

/** @brief Base address of DSP2ARM1 mailbox peripheral data registers */
#define CSL_MBX_DSP2ARM1_DATA_REGS  (0xF804u)

/** @brief Base address of DSP2ARM2 mailbox peripheral data registers */
#define CSL_MBX_DSP2ARM2_DATA_REGS  (0xF808u)

/** @brief Base address of ARM2DSP1 mailbox peripheral data registers */
#define CSL_MBX_ARM2DSP1_DATA_REGS  (0xF800u)

/** @brief Base address of ARM2DSP2 mailbox peripheral data registers */
#define CSL_MBX_ARM2DSP2_DATA_REGS  (0xF812u)

/** @brief Base address of DSP2ARM1 mailbox peripheral flag registers */
#define CSL_MBX_DSP2ARM1_INTR_REGS  (0xF80Eu)

/** @brief Base address of DSP2ARM2 mailbox peripheral flag registers */
#define CSL_MBX_DSP2ARM2_INTR_REGS  (0xF810u)

/** @brief Base address of ARM2DSP1 mailbox peripheral flag registers */
#define CSL_MBX_ARM2DSP1_INTR_REGS  (0xF80Cu)

/** @brief Base address of ARM2DSP2 mailbox peripheral flag registers */
#define CSL_MBX_ARM2DSP2_INTR_REGS  (0xF816u)

/** @brief Base address of GPTIMER peripheral flag registers */
#define CSL_GPTIMER_1_REGS          (0x008A00u)

#define CSL_GPTIMER_2_REGS          (0x008E00u)

#define CSL_GPTIMER_3_REGS          (0x009200u)

#define CSL_GPTIMER_4_REGS          (0x009600u)

#define CSL_GPTIMER_5_REGS          (0x009A00u)

#define CSL_GPTIMER_6_REGS          (0x009E00u)

#define CSL_GPTIMER_7_REGS          (0x00BA00u)

#define CSL_GPTIMER_8_REGS          (0x00EA00u)

/** @brief Base address of WDTimer peripheral flag registers */
#define CSL_WDT_1_REGS              (0x003400u)

/** @brief Base address of ADCC peripheral Control registers */
#define CSL_ADCC_1_REGS             (0x00AC00u)

/** @brief Base address of MCSI pheripheral registers */
#define CSL_MCSI_1_REGS             (0x009400u)

#define CSL_MCSI_2_REGS             (0x009000u)

/** @brief Base address of GPIO peripheral registers */
#define CSL_GPIO_1_REGS             (0xF200)

#define CSL_GPIO_2_REGS             (0xF600)

#define CSL_GPIO_3_REGS             (0xCA00)

#define CSL_GPIO_4_REGS             (0xCE00)

/** @brief Base address of WDTimer peripheral flag registers */
#define CSL_WDT_1_REGS              (0x003400u)

/** @brief Base address of SPI peripheral registers */
#define CSL_SPI_1_REGS              (0x008600u)

/**************************************************************************\
* Peripheral Instance definitions.
\**************************************************************************/
/** @brief Peripheral Instances of UART */
#define     CSL_UART_1  (0)  /** Instance 1 of UART */

#define     CSL_UART_2  (1)  /** Instance 2 of UART */

#define     CSL_UART_3  (2)  /** Instance 3 of UART */