csl_clkrst.h

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/** @mainpage CLKRST CSL (DSP side) * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for the CLKRST module across various devices. The CSL developer is expected to refer to this document while designing APIs for these modules. Some of the listed APIs may not be applicable to a given CLKRST module. While in other cases this list of APIs may not be sufficient to cover all the features of a particular CLKRST Module. The CSL developer should use his discretion in designing new APIs or extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations *   -# CSL:    Chip Support Library *   -# API:    Application Programmer Interface *   -# CLKRST: Clock Generator & System Reset * * @subsection References *    -# CSL-001-DES, CSL 3.x Design Specification Document Version 1.03 *    -# SWPU062C, OMAP1610 Multimedia Processor Technical Reference Manual, November 2003, Chapter 2 Section 4 * *//** @file csl_clkrst.h * *  @brief    Header file for functional layer of CSL * *  Description *    - The different enumerations, structure definitions and function declarations * *  Modification 1 *    - modified on: 14/04/2004 *    - reason: Created the initial version * *  @date 29th March, 2004 *  @author Sumant S. NaikKhanvte */#ifndef _CSL_CLKRST_H_#define _CSL_CLKRST_H_#ifdef __cplusplusextern "C" {#endif#include <csl.h>#include <cslr_clkrst.h>/**************************************************************************\* CLKRST global macro declarations\**************************************************************************//**************************************************************************\* CLKRST global typedef declarations\**************************************************************************//** @brief Enumeration for CLKRST hardware control commands */typedef enum {	/** send the selected domains into reset : argument : @a Uint16 * */	CSL_CLKRST_CMD_RESET_IN  =  1,	/** bring the selected domains out of reset : argument : @a Uint16 * */	CSL_CLKRST_CMD_RESET_OUT,	/** enable the selected clocks. The argument is a bit vector formed by bitwise-ORing 1 or more members of @a CSL_ClkrstModule : argument : @a Uint16 * */	CSL_CLKRST_CMD_CLK_ENABLE,	/** disable the selected clocks. The argument is a bit vector formed by bitwise-ORing 1 or more members of @a CSL_ClkrstModule : argument : @a Uint16 * */	CSL_CLKRST_CMD_CLK_DISABLE} CSL_ClkrstHwControlCmd;/** @brief Enumeration for CLKRST hardware status queries */typedef enum {	/** query for the status of CLKRST (source of reset & clock scheme) : argument : @a CSL_ClkrstStatus * */	CSL_CLKRST_QUERY_STATUS  =  1,	/** query the existing setting of the clock enable/disable. The argument returned is a bitwise-ORed bitmask of @a CSL_ClkrstModule : argument : @a Uint16 * */	CSL_CLKRST_QUERY_CLKIDLEENTRY_SETTING} CSL_ClkrstHwStatusQuery;/** @brief Enumeration for all the idle-entry & enable/disable clocks of modules */typedef enum {	/** UART module */	CSL_CLKRST_MODULE_UART  =  (1 << 0),	/** Peripheral module */	CSL_CLKRST_MODULE_PER   =  (1 << 1),	/** Reference peripheral module */	CSL_CLKRST_MODULE_XORP  =  (1 << 2),	/** Watchdog timer module */	CSL_CLKRST_MODULE_WDT   =  (1 << 3)} CSL_ClkrstModule;/** @brief Enumeration for CLKRST clocking schemes */typedef enum {	/** Fully synchronous clocking scheme */	CSL_CLKRST_CLKSCHEME_FULLSYNC  =  CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_FULL_SYNC,	/** Synchronous scalable clocking scheme */	CSL_CLKRST_CLKSCHEME_SYNCSCAL  =  CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_SYNC_SCAL,	/** bypass */	CSL_CLKRST_CLKSCHEME_BYPASS    =  CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_BYPASS,	/** Mixed mode 3 clocking scheme */	CSL_CLKRST_CLKSCHEME_MM3       =  CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_MM3,	/** Mixed mode 4 clocking scheme */	CSL_CLKRST_CLKSCHEME_MM4       =  CSL_CLKRST_DSP_SYSST_CLOCK_SELECT_MM4} CSL_ClkrstClkScheme;/** @brief Enumeration for input clock sources */typedef enum {	/** DSPTIM_CK supplied by input reference clock */	CSL_CLKRST_CLKSRC_TIM_IPREFCK   =  CSL_FMKT(CLKRST_DSP_CKCTL_TIMXO, IP_REF_CK),	/** DSPTIM_CK supplied by CKGEN2 clock */	CSL_CLKRST_CLKSRC_TIM_CKGEN2    =  CSL_FMKT(CLKRST_DSP_CKCTL_TIMXO, CK_GEN2)} CSL_ClkrstClkSrc;/** @brief Enumeration for MPU's idle status */typedef enum {	/** MPU megacell is in global-idle state */	CSL_CLKRST_MPUSTATUS_IDLE    =  CSL_CLKRST_DSP_SYSST_IDLE_ARM_IDLE,	/** MPU megacell is active */	CSL_CLKRST_MPUSTATUS_ACTIVE  =  CSL_CLKRST_DSP_SYSST_IDLE_ARM_ACTIVE} CSL_ClkrstMpuStatus;/** @brief Enumeration for the different reset domains controlled through software */typedef enum {	/** peripherals under software reset control */	CSL_CLKRST_RESETTYPE_PER    =  CSL_FMKT(CLKRST_DSP_RSTCT2_PER_EN, ENABLED),	/** peripherals under software & watch dog reset control */	CSL_CLKRST_RESETTYPE_WDPER  =  CSL_FMKT(CLKRST_DSP_RSTCT2_WD_PER_EN, ENABLED)} CSL_ClkrstResetType;/** @brief Enumeration for the different sources for reset */typedef enum {	/** Power-on reset */	CSL_CLKRST_RESETSRC_POR    =  CSL_FMKT(CLKRST_DSP_SYSST_POR, YES),	/** external reset */	CSL_CLKRST_RESETSRC_EXT    =  CSL_FMKT(CLKRST_DSP_SYSST_EXT_RST, YES),	/** MPU watchdog timer reset */	CSL_CLKRST_RESETSRC_MPUWD  =  CSL_FMKT(CLKRST_DSP_SYSST_ARM_WDRST, YES),	/** global software reset */	CSL_CLKRST_RESETSRC_GLOB   =  CSL_FMKT(CLKRST_DSP_SYSST_GLOB_SWRST, YES),	/** DSP watchdog timer reset */	CSL_CLKRST_RESETSRC_DSPWD  =  CSL_FMKT(CLKRST_DSP_SYSST_DSP_WDRST, YES)} CSL_ClkrstResetSrc;/** @brief This object contains the reference to the instance of CLKRST opened *  using the @a CSL_clkrstOpen(). * *  The pointer to this, is passed to all CLKRST CSL APIs. */typedef struct CSL_ClkrstObj {	/** This is a pointer to the registers of the instance of CLKRST     *  referred to by this object     */	CSL_ClkrstRegsOvly regs;	/** This is the instance of CLKRST being referred to by this object  */	CSL_InstNum  	perNum;} CSL_ClkrstObj;typedef struct CSL_ClkrstObj *CSL_ClkrstHandle;/** @brief This will have the base-address information for the peripheral *  instance */typedef struct {	/** Base-address of the Configuration registers of the peripheral	 */	CSL_ClkrstRegsOvly	regs;} CSL_ClkrstBaseAddress;/** @brief Module specific parameters. Present implementation doesn't have *  any module specific parameters. */typedef struct{	/** Bit mask to be used for module specific parameters.         *  The below declaration is just a place-holder for future 	 *  implementation.	 */	CSL_BitMask16   flags;} CSL_ClkrstParam;/** @brief Module specific context information. Present implementation doesn't have *  any Context information. */typedef struct {	/** Context information of CLKRST.         *  The below declaration is just a place-holder for future 	 *  implementation. 	 */    Uint16	contextInfo;} CSL_ClkrstContext;/** @brief part of @a CSL_ClkrstHwSetup used to configure clock dividers * * This structure is used to configure the clock dividers for the different clocks. The permissible values are 0-3. The clock is divided by 2^(value) */typedef struct CSL_ClkrstClkDiv {	/** divider value for peripheral clock */	Uint8  perDiv;} CSL_ClkrstClkDiv;/** @brief main structure that is used to setup the CLKRST * * This structure is used to setup or obtain the existing setup of CLKRST using @a CSL_clkrstHwSetup() & @a CSL_clkrstGetHwSetup() functions respectively. If a particular member pointer is null, then these functions do not setup or get the setup of the corresponding part of CLKRST respectively */typedef struct CSL_ClkrstHwSetup {	/** This pointer is used to configure the sources for Timer clock pins */	CSL_ClkrstClkSrc  *clkSourcePtr;	/** This pointer is used to configure the idle entry modes of different clock pins. This takes a bitmask made by bitwise-ORing @a CSL_ClkrstModule except @a CSL_CLKRST_MODULE_UART */	Uint16            *clkIdleEntryPtr;	/** pointer to the structure that hold information about clock dividers needed */	CSL_ClkrstClkDiv  *clkDivPtr;} CSL_ClkrstHwSetup;typedef struct CSL_ClkrstStatus {	/** the clock scheme used for the OMAP Gigacell */	CSL_ClkrstClkScheme  clkScheme;	/** status of the reset source for OMAP Gigacell; the returned value will be a member of @CSL_ClkrstResetSrc */	Uint8                status;	/** idle mode status of the MPU */	CSL_ClkrstMpuStatus  mpuStatus;} CSL_ClkrstStatus;/** * @brief   The config-structure * * Used to configure the clkrst using CSL_clkrstHwSetupRaw() function */typedef struct  {    Uint16 DSP_CKCTL;    /**< DSP clock control register */    Uint16 DSP_IDLECT1;  /**< DSP idle control register 1 */    Uint16 DSP_IDLECT2;  /**< DSP idle control register 2 */    Uint16 DSP_RSTCT2;   /**< DSP reset control register 2 */    Uint16 DSP_SYSST;    /**< DSP system status register */} CSL_ClkrstConfig;/** The default value for @a CSL_ClkrstHwSetup structure */#define CSL_CLKRST_HWSETUP_DEFAULTS { \           NULL,                      \           NULL,                      \           NULL                       \        }/** The default value for @a CSL_ClkrstClkDiv structure */#define CSL_CLKRST_CLKDIV_DEFAULTS { \	   0,                        \	   0,                        \	   0                         \	}/** The default value for @a CSL_ClkrstConfig structure */#define CSL_CLKRST_CONFIG_DEFAULTS {          \	    CSL_CLKRST_DSP_CKCTL_RESETVAL,    \	    CSL_CLKRST_DSP_IDLECT1_RESETVAL,  \	    CSL_CLKRST_DSP_IDLECT2_RESETVAL,  \	    CSL_CLKRST_DSP_RSTCT2_RESETVAL,   \	    CSL_CLKRST_DSP_SYSST_RESETVAL     \}/** @brief Peripheral specific initialization function. * * This is the peripheral specific intialization function. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't touches * the hardware. * * <b> Usage Constraints: </b> * This function should be called before using any of the CSL APIs in the CLKRST * module. * *  Note: As CLKRST doesn't have any context based information, currently, the function *  just returns CSL_SOK. User is expected to pass NULL in the function call. * * @b Example: * @verbatim   ...

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