cslr_mcbsp.h

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/*****************************************************\ *  Copyright 2003, Texas Instruments Incorporated.  * *  All rights reserved.                             * *  Restricted rights to use, duplicate or disclose  * *  this   code   are  granted   through  contract.  *\*****************************************************//*  @(#) PSP/CSL 3.00.01.00[5912PG1_0] (2003-10-15)  */#ifndef _CSLR_MCBSP_002_H_#define _CSLR_MCBSP_002_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    volatile Uint16 DRR2;    volatile Uint16 DRR1;    volatile Uint16 DXR2;    volatile Uint16 DXR1;    volatile Uint16 SPCR2;    volatile Uint16 SPCR1;    volatile Uint16 RCR2;    volatile Uint16 RCR1;    volatile Uint16 XCR2;    volatile Uint16 XCR1;    volatile Uint16 SRGR2;    volatile Uint16 SRGR1;    volatile Uint16 MCR2;    volatile Uint16 MCR1;    volatile Uint16 RCERA;    volatile Uint16 RCERB;    volatile Uint16 XCERA;    volatile Uint16 XCERB;    volatile Uint16 PCR;    volatile Uint16 RCERC;    volatile Uint16 RCERD;    volatile Uint16 XCERC;    volatile Uint16 XCERD;    volatile Uint16 RCERE;    volatile Uint16 RCERF;    volatile Uint16 XCERE;    volatile Uint16 XCERF;    volatile Uint16 RCERG;    volatile Uint16 RCERH;    volatile Uint16 XCERG;    volatile Uint16 XCERH;} CSL_McbspRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile ioport CSL_McbspRegs  * CSL_McbspRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************/  /* CSL_MCBSP_DRR2 */#define CSL_MCBSP_DRR2_DRR2_MASK      (0xFFFFu)#define CSL_MCBSP_DRR2_DRR2_SHIFT     (0x0000u)#define CSL_MCBSP_DRR2_DRR2_RESETVAL  (0x0000u)#define CSL_MCBSP_DRR2_RESETVAL       (0x0000u)  /* CSL_MCBSP_DRR1 */#define CSL_MCBSP_DRR1_DRR1_MASK      (0xFFFFu)#define CSL_MCBSP_DRR1_DRR1_SHIFT     (0x0000u)#define CSL_MCBSP_DRR1_DRR1_RESETVAL  (0x0000u)#define CSL_MCBSP_DRR1_RESETVAL       (0x0000u)  /* CSL_MCBSP_DXR2 */#define CSL_MCBSP_DXR2_DXR2_MASK      (0xFFFFu)#define CSL_MCBSP_DXR2_DXR2_SHIFT     (0x0000u)#define CSL_MCBSP_DXR2_DXR2_RESETVAL  (0x0000u)#define CSL_MCBSP_DXR2_RESETVAL       (0x0000u)  /* CSL_MCBSP_DXR1 */#define CSL_MCBSP_DXR1_DXR1_MASK      (0xFFFFu)#define CSL_MCBSP_DXR1_DXR1_SHIFT     (0x0000u)#define CSL_MCBSP_DXR1_DXR1_RESETVAL  (0x0000u)#define CSL_MCBSP_DXR1_RESETVAL       (0x0000u)  /* CSL_MCBSP_SPCR2 */#define CSL_MCBSP_SPCR2_FREE_MASK     (0x0200u)#define CSL_MCBSP_SPCR2_FREE_SHIFT    (0x0009u)#define CSL_MCBSP_SPCR2_FREE_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR2_SOFT_MASK     (0x0100u)#define CSL_MCBSP_SPCR2_SOFT_SHIFT    (0x0008u)#define CSL_MCBSP_SPCR2_SOFT_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR2_FRST_MASK     (0x0080u)#define CSL_MCBSP_SPCR2_FRST_SHIFT    (0x0007u)#define CSL_MCBSP_SPCR2_FRST_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR2_GRST_MASK     (0x0040u)#define CSL_MCBSP_SPCR2_GRST_SHIFT    (0x0006u)#define CSL_MCBSP_SPCR2_GRST_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR2_XINTM_MASK    (0x0030u)#define CSL_MCBSP_SPCR2_XINTM_SHIFT   (0x0004u)#define CSL_MCBSP_SPCR2_XINTM_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SPCR2_XSYNCERR_MASK (0x0008u)#define CSL_MCBSP_SPCR2_XSYNCERR_SHIFT                                    \          (0x0003u)#define CSL_MCBSP_SPCR2_XSYNCERR_RESETVAL                                 \          (0x0000u)#define CSL_MCBSP_SPCR2_XSYNCERR_CLEAR                                    \          (0x0000u)#define CSL_MCBSP_SPCR2_XEMPTY_MASK   (0x0004u)#define CSL_MCBSP_SPCR2_XEMPTY_SHIFT  (0x0002u)#define CSL_MCBSP_SPCR2_XEMPTY_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_SPCR2_XRDY_MASK     (0x0002u)#define CSL_MCBSP_SPCR2_XRDY_SHIFT    (0x0001u)#define CSL_MCBSP_SPCR2_XRDY_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR2_XRST_MASK     (0x0001u)#define CSL_MCBSP_SPCR2_XRST_SHIFT    (0x0000u)#define CSL_MCBSP_SPCR2_XRST_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR2_RESETVAL      (0x0000u)  /* CSL_MCBSP_SPCR1 */#define CSL_MCBSP_SPCR1_DLB_MASK      (0x8000u)#define CSL_MCBSP_SPCR1_DLB_SHIFT     (0x000Fu)#define CSL_MCBSP_SPCR1_DLB_RESETVAL  (0x0000u)#define CSL_MCBSP_SPCR1_RJUST_MASK    (0x6000u)#define CSL_MCBSP_SPCR1_RJUST_SHIFT   (0x000Du)#define CSL_MCBSP_SPCR1_RJUST_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SPCR1_CLKSTP_MASK   (0x1800u)#define CSL_MCBSP_SPCR1_CLKSTP_SHIFT  (0x000Bu)#define CSL_MCBSP_SPCR1_CLKSTP_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_SPCR1_DXENA_MASK    (0x0080u)#define CSL_MCBSP_SPCR1_DXENA_SHIFT   (0x0007u)#define CSL_MCBSP_SPCR1_DXENA_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SPCR1_RINTM_MASK    (0x0030u)#define CSL_MCBSP_SPCR1_RINTM_SHIFT   (0x0004u)#define CSL_MCBSP_SPCR1_RINTM_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SPCR1_RSYNCERR_MASK (0x0008u)#define CSL_MCBSP_SPCR1_RSYNCERR_SHIFT                                    \          (0x0003u)#define CSL_MCBSP_SPCR1_RSYNCERR_RESETVAL                                 \          (0x0000u)#define CSL_MCBSP_SPCR1_RSYNCERR_CLEAR                                    \          (0x0000u)#define CSL_MCBSP_SPCR1_RFULL_MASK    (0x0004u)#define CSL_MCBSP_SPCR1_RFULL_SHIFT   (0x0002u)#define CSL_MCBSP_SPCR1_RFULL_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SPCR1_RRDY_MASK     (0x0002u)#define CSL_MCBSP_SPCR1_RRDY_SHIFT    (0x0001u)#define CSL_MCBSP_SPCR1_RRDY_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR1_RRST_MASK     (0x0001u)#define CSL_MCBSP_SPCR1_RRST_SHIFT    (0x0000u)#define CSL_MCBSP_SPCR1_RRST_RESETVAL (0x0000u)#define CSL_MCBSP_SPCR1_RESETVAL      (0x0000u)  /* CSL_MCBSP_RCR2 */#define CSL_MCBSP_RCR2_RPHASE_MASK    (0x8000u)#define CSL_MCBSP_RCR2_RPHASE_SHIFT   (0x000Fu)#define CSL_MCBSP_RCR2_RPHASE_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_RCR2_RFRLEN2_MASK   (0x7F00u)#define CSL_MCBSP_RCR2_RFRLEN2_SHIFT  (0x0008u)#define CSL_MCBSP_RCR2_RFRLEN2_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_RCR2_RWDLEN2_MASK   (0x00E0u)#define CSL_MCBSP_RCR2_RWDLEN2_SHIFT  (0x0005u)#define CSL_MCBSP_RCR2_RWDLEN2_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_RCR2_RWDLEN2_8BITS  (0x0000u)#define CSL_MCBSP_RCR2_RWDLEN2_12BITS (0x0001u)#define CSL_MCBSP_RCR2_RWDLEN2_16BITS (0x0002u)#define CSL_MCBSP_RCR2_RWDLEN2_20BITS (0x0003u)#define CSL_MCBSP_RCR2_RWDLEN2_24BITS (0x0004u)#define CSL_MCBSP_RCR2_RWDLEN2_32BITS (0x0005u)#define CSL_MCBSP_RCR2_RCOMPAND_MASK  (0x0018u)#define CSL_MCBSP_RCR2_RCOMPAND_SHIFT (0x0003u)#define CSL_MCBSP_RCR2_RCOMPAND_RESETVAL                                  \          (0x0000u)#define CSL_MCBSP_RCR2_RFIG_MASK      (0x0004u)#define CSL_MCBSP_RCR2_RFIG_SHIFT     (0x0002u)#define CSL_MCBSP_RCR2_RFIG_RESETVAL  (0x0000u)#define CSL_MCBSP_RCR2_RDATDLY_MASK   (0x0003u)#define CSL_MCBSP_RCR2_RDATDLY_SHIFT  (0x0000u)#define CSL_MCBSP_RCR2_RDATDLY_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_RCR2_RESETVAL       (0x0000u)  /* CSL_MCBSP_RCR1 */#define CSL_MCBSP_RCR1_RFRLEN1_MASK   (0x7F00u)#define CSL_MCBSP_RCR1_RFRLEN1_SHIFT  (0x0008u)#define CSL_MCBSP_RCR1_RFRLEN1_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_RCR1_RWDLEN1_MASK   (0x00E0u)#define CSL_MCBSP_RCR1_RWDLEN1_SHIFT  (0x0005u)#define CSL_MCBSP_RCR1_RWDLEN1_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_RCR1_RWDLEN1_8BITS  (0x0000u)#define CSL_MCBSP_RCR1_RWDLEN1_12BITS (0x0001u)#define CSL_MCBSP_RCR1_RWDLEN1_16BITS (0x0002u)#define CSL_MCBSP_RCR1_RWDLEN1_20BITS (0x0003u)#define CSL_MCBSP_RCR1_RWDLEN1_24BITS (0x0004u)#define CSL_MCBSP_RCR1_RWDLEN1_32BITS (0x0005u)#define CSL_MCBSP_RCR1_RESETVAL       (0x0000u)  /* CSL_MCBSP_XCR2 */#define CSL_MCBSP_XCR2_XPHASE_MASK    (0x8000u)#define CSL_MCBSP_XCR2_XPHASE_SHIFT   (0x000Fu)#define CSL_MCBSP_XCR2_XPHASE_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_XCR2_XFRLEN2_MASK   (0x7F00u)#define CSL_MCBSP_XCR2_XFRLEN2_SHIFT  (0x0008u)#define CSL_MCBSP_XCR2_XFRLEN2_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_XCR2_XWDLEN2_MASK   (0x00E0u)#define CSL_MCBSP_XCR2_XWDLEN2_SHIFT  (0x0005u)#define CSL_MCBSP_XCR2_XWDLEN2_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_XCR2_XWDLEN2_8BITS  (0x0000u)#define CSL_MCBSP_XCR2_XWDLEN2_12BITS (0x0001u)#define CSL_MCBSP_XCR2_XWDLEN2_16BITS (0x0002u)#define CSL_MCBSP_XCR2_XWDLEN2_20BITS (0x0003u)#define CSL_MCBSP_XCR2_XWDLEN2_24BITS (0x0004u)#define CSL_MCBSP_XCR2_XWDLEN2_32BITS (0x0005u)#define CSL_MCBSP_XCR2_XCOMPAND_MASK  (0x0018u)#define CSL_MCBSP_XCR2_XCOMPAND_SHIFT (0x0003u)#define CSL_MCBSP_XCR2_XCOMPAND_RESETVAL                                  \          (0x0000u)#define CSL_MCBSP_XCR2_XFIG_MASK      (0x0004u)#define CSL_MCBSP_XCR2_XFIG_SHIFT     (0x0002u)#define CSL_MCBSP_XCR2_XFIG_RESETVAL  (0x0000u)#define CSL_MCBSP_XCR2_XDATDLY_MASK   (0x0003u)#define CSL_MCBSP_XCR2_XDATDLY_SHIFT  (0x0000u)#define CSL_MCBSP_XCR2_XDATDLY_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_XCR2_RESETVAL       (0x0000u)  /* CSL_MCBSP_XCR1 */#define CSL_MCBSP_XCR1_XFRLEN1_MASK   (0x7F00u)#define CSL_MCBSP_XCR1_XFRLEN1_SHIFT  (0x0008u)#define CSL_MCBSP_XCR1_XFRLEN1_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_XCR1_XWDLEN1_MASK   (0x00E0u)#define CSL_MCBSP_XCR1_XWDLEN1_SHIFT  (0x0005u)#define CSL_MCBSP_XCR1_XWDLEN1_RESETVAL                                   \          (0x0000u)#define CSL_MCBSP_XCR1_XWDLEN1_8BITS  (0x0000u)#define CSL_MCBSP_XCR1_XWDLEN1_12BITS (0x0001u)#define CSL_MCBSP_XCR1_XWDLEN1_16BITS (0x0002u)#define CSL_MCBSP_XCR1_XWDLEN1_20BITS (0x0003u)#define CSL_MCBSP_XCR1_XWDLEN1_24BITS (0x0004u)#define CSL_MCBSP_XCR1_XWDLEN1_32BITS (0x0005u)#define CSL_MCBSP_XCR1_RESETVAL       (0x0000u)  /* CSL_MCBSP_SRGR2 */#define CSL_MCBSP_SRGR2_GSYNC_MASK    (0x8000u)#define CSL_MCBSP_SRGR2_GSYNC_SHIFT   (0x000Fu)#define CSL_MCBSP_SRGR2_GSYNC_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SRGR2_CLKSP_MASK    (0x4000u)#define CSL_MCBSP_SRGR2_CLKSP_SHIFT   (0x000Eu)#define CSL_MCBSP_SRGR2_CLKSP_RESETVAL                                    \          (0x0000u)#define CSL_MCBSP_SRGR2_CLKSM_MASK    (0x2000u)#define CSL_MCBSP_SRGR2_CLKSM_SHIFT   (0x000Du)#define CSL_MCBSP_SRGR2_CLKSM_RESETVAL                                    \          (0x0001u)#define CSL_MCBSP_SRGR2_FSGM_MASK     (0x1000u)#define CSL_MCBSP_SRGR2_FSGM_SHIFT    (0x000Cu)#define CSL_MCBSP_SRGR2_FSGM_RESETVAL (0x0000u)#define CSL_MCBSP_SRGR2_FPER_MASK     (0x0FFFu)#define CSL_MCBSP_SRGR2_FPER_SHIFT    (0x0000u)#define CSL_MCBSP_SRGR2_FPER_RESETVAL (0x0000u)#define CSL_MCBSP_SRGR2_RESETVAL      (0x2000u)  /* CSL_MCBSP_SRGR1 */#define CSL_MCBSP_SRGR1_FWID_MASK     (0xFF00u)#define CSL_MCBSP_SRGR1_FWID_SHIFT    (0x0008u)#define CSL_MCBSP_SRGR1_FWID_RESETVAL (0x0000u)#define CSL_MCBSP_SRGR1_CLKGDV_MASK   (0x00FFu)#define CSL_MCBSP_SRGR1_CLKGDV_SHIFT  (0x0000u)#define CSL_MCBSP_SRGR1_CLKGDV_RESETVAL                                   \          (0x0001u)#define CSL_MCBSP_SRGR1_RESETVAL      (0x0001u)  /* CSL_MCBSP_MCR2 */#define CSL_MCBSP_MCR2_XMCME_MASK     (0x0200u)#define CSL_MCBSP_MCR2_XMCME_SHIFT    (0x0009u)#define CSL_MCBSP_MCR2_XMCME_RESETVAL (0x0000u)#define CSL_MCBSP_MCR2_XMCME_PARTITIONS2                                  \          (0x0000u)#define CSL_MCBSP_MCR2_XMCME_PARTITIONS8                                  \
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