mcbsp_init.c

来自「dsp在音频处理中的运用」· C语言 代码 · 共 93 行

#include <soc.h>
#include <csl_mcbsp.h>


void sMcbsp1_init(CSL_McbspHandle *hMcbsp1ptr);
{   CSL_Status      status;
    CSL_mcbspInit(NULL);
	*hMcbsp1ptr = CSL_mcbspOpen(&myMcbspObj, CSL_MCBSP_1, NULL, &status);

}


void mcbsp1_init(hMcbsp1)
{  

CSL_BitMask16   ctrlMask;
CSL_McbspGlobalSetup gblCfg = {
    CSL_MCBSP_IOMODE_TXDIS_RXDIS,
    CSL_MCBSP_DLBMODE_OFF,
    CSL_MCBSP_CLKSTP_DISABLE
    };

CSL_McbspDataSetup rcvDataCfg = {
    CSL_MCBSP_PHASE_SINGLE,
    CSL_MCBSP_WORDLEN_16,
    1, /* FRMLEN1 */
    CSL_MCBSP_WORDLEN_8, /* Default value */
    1, /* FRMLEN2 */
    CSL_MCBSP_FRMSYNC_DETECT,
    CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
    CSL_MCBSP_DATADELAY_0_BIT, /* CSL_MCBSP_DATADELAY_0_BIT */ /* ka */
    CSL_MCBSP_RJUSTDXENA_RJUST_RZF,
    CSL_MCBSP_INTMODE_ON_READY    ///?
};

CSL_McbspDataSetup xmtDataCfg = {
    CSL_MCBSP_PHASE_SINGLE,
    CSL_MCBSP_WORDLEN_16,
    1, /* FRMLEN1 */
    CSL_MCBSP_WORDLEN_8, /* Default value */
    1, /* FRMLEN2 */
    CSL_MCBSP_FRMSYNC_DETECT,
    CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
    CSL_MCBSP_DATADELAY_0_BIT, /* CSL_MCBSP_DATADELAY_0_BIT */ /* ka */
    CSL_MCBSP_RJUSTDXENA_DXENA_OFF,
    CSL_MCBSP_INTMODE_ON_READY
};

CSL_McbspClkSetup clkCfg = {
    CSL_MCBSP_FSCLKMODE_EXTERNAL, /* XMT Frame-sync */
    CSL_MCBSP_FSCLKMODE_EXTERNAL, /* RCV Frame-sync */
    CSL_MCBSP_TXRXCLKMODE_EXTERNAL, /* XMT clock */
    CSL_MCBSP_TXRXCLKMODE_EXTERNAL, /* RCV clock */
    CSL_MCBSP_FSPOL_ACTIVE_HIGH,   /* XMT Frame-sync Active High */
    CSL_MCBSP_FSPOL_ACTIVE_HIGH,   /* RCV Frame-sync Active High */
    CSL_MCBSP_CLKPOL_TX_RISING_EDGE,   /* XMT clock Rising Edge */
    CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,   /* RCV clock Falling Edge */
    1,  /* Frame-sync pulse width = 1 bit */
    15, /* Frame-sync pulse period = 16 bits */
    1,  /* CLKGDIV = 1 means divide by input clock by 2 */
    CSL_MCBSP_SRGCLK_CLKS, /* SCLKME = 0, CLKSM = 0 */
    CSL_MCBSP_CLKPOL_SRG_RISING_EDGE, /* CLKS pin signal Rising Edge */
    CSL_MCBSP_TXFSMODE_DXRCOPY, /* If FSXM = 1, XMT Frame-sync
                                      when DXR copied to XSR */
    CSL_MCBSP_CLKGSYNCMODE_OFF /* GSYNC = 0 means no clock synchronisation */
};

CSL_McbspMulChSetup mulChCfg = CSL_MCBSP_MULTICHAN_DEFAULTS;

CSL_McbspHwSetup mcbspHwCfg = {
    &gblCfg,
    &rcvDataCfg,
    &xmtDataCfg,
    &clkCfg,
    &mulChCfg,
    CSL_MCBSP_EMU_STOP,
    NULL
};

   ctrlMask =   CSL_MCBSP_CTRL_SRG_DISABLE
               | CSL_MCBSP_CTRL_FSYNC_DISABLE
               | CSL_MCBSP_CTRL_TX_DISABLE
               | CSL_MCBSP_CTRL_RX_DISABLE;
    CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL, &ctrlMask);

    /* Program MCBSP control registers and wait for 2 clock cycles */
    CSL_mcbspHwSetup(hMcbsp, &mcbspHwCfg);
    WAIT_FOR_2_CLK;


}