csl_clkrst.h

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/** @mainpage CLKRST CSL (MPU side)
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for the CLKRST module across various devices. The CSL developer is expected to refer to this document while designing APIs for these modules. Some of the listed APIs may not be applicable to a given CLKRST module. While in other cases this list of APIs may not be sufficient to cover all the features of a particular CLKRST Module. The CSL developer should use his discretion in designing new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:    Chip Support Library
 *   -# API:    Application Programmer Interface
 *   -# CLKRST: Clock Generator & System Reset
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification Document Version 1.03
 *    -# SWPU062C, OMAP1610 Multimedia Processor Technical Reference Manual, November 2003, Chapter 2 Section 4
 *
 */

/** @file csl_clkrst.h
 *
 *  @brief    Header file for functional layer of CSL
 *
 *  Description
 *    - The different enumerations, structure definitions and function declarations
 *
 *  Modification 1
 *    - modified on: 14/04/2004
 *    - reason: Created the initial version
 *
 *  @date 29th March, 2004
 *  @author Sumant S. NaikKhanvte
 */

#ifndef _CSL_CLKRST_H_
#define _CSL_CLKRST_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <cslr_clkrst.h>


/**************************************************************************\
* CLKRST global macro declarations
\**************************************************************************/

/**************************************************************************\
* CLKRST global typedef declarations
\**************************************************************************/


/** @brief Enumeration for CLKRST hardware control commands */
typedef enum {
	/** send the selected domains into reset : argument : @a Uint16 * */
	CSL_CLKRST_CMD_RESET_IN  =  1,
	/** bring the selected domains out of reset : argument : @a Uint16 * */
	CSL_CLKRST_CMD_RESET_OUT,
	/** enable the selected clocks. The argument is a bit vector formed by bitwise-ORing 1 or more members of @a CSL_ClkrstModule except @a CSL_CLKRST_MODULE_DPLL & @a CSL_CLKRST_MODULE_IF  : argument : @a Uint16 * */
	CSL_CLKRST_CMD_CLK_ENABLE,
	/** disable the selected clocks. The argument is a bit vector formed by bitwise-ORing 1 or more members of @a CSL_ClkrstModule except @a CSL_CLKRST_MODULE_DPLL & @a CSL_CLKRST_MODULE_IF : argument : @a Uint16 * */
	CSL_CLKRST_CMD_CLK_DISABLE
} CSL_ClkrstHwControlCmd;


/** @brief Enumeration for CLKRST hardware status queries */
typedef enum {
	/** query for the source which caused the reset : argument : @a Uint16 * */
	CSL_CLKRST_QUERY_RESET_STATUS  =  1,
	/** query the existing setting of the clock enable/disable. The argument returned is a bitwise-ORed bitmask of @a CSL_ClkrstModule : argument : @a Uint16 * */
	CSL_CLKRST_QUERY_CLKIDLEENTRY_SETTING
} CSL_ClkrstHwStatusQuery;


/** @brief Enumeration for the different sources for a domain's CLKOUT pin. There are 3 domains here. They are: MPU, DSP & TC */
typedef enum {
	/** the domain's clockout will be sourced through the DSP MMU clock. Does not apply for the other 2 domains */
	CSL_CLKRST_CKOUTTYPE_DSP_MMUCK  =  0,
	/** the domain's clockout will be sourced through the domains's CLK_GEN clock */
	CSL_CLKRST_CKOUTTYPE_DOMAIN_CKGEN,
	/** the domain's clockout will be sourced through the domains's output clock */
	CSL_CLKRST_CKOUTTYPE_DOMAIN_CK,
	/** the domain's clockout will be sourced through the reference clock divided by 14 (used only for MPU & DSP domains) */
	CSL_CLKRST_CKOUTTYPE_CKREFBY14
} CSL_ClkrstCkoutType;


/** @brief Enumeration for all the idle-entry & enable/disable clocks of modules */
typedef enum {
	/** MPU module */
	CSL_CLKRST_MODULE_MPU   =  (1 << 0),
	/** GPIO module */
	CSL_CLKRST_MODULE_GPIO  =  (1 << 14),
	/** DMA module */
	CSL_CLKRST_MODULE_DMA   =  (1 << 1),
	/** Timer module */
	CSL_CLKRST_MODULE_TIM   =  (1 << 2),
	/** API module */
	CSL_CLKRST_MODULE_API   =  (1 << 3),
	/** DPLL module */
	CSL_CLKRST_MODULE_DPLL  =  (1 << 4),
	/** IF module */
	CSL_CLKRST_MODULE_IF    =  (1 << 5),
	/** LCD module */
	CSL_CLKRST_MODULE_LCD   =  (1 << 6),
	/** peripheral module */
	CSL_CLKRST_MODULE_PER   =  (1 << 7),
	/** reference peripheral module */
	CSL_CLKRST_MODULE_XORP  =  (1 << 8),
	/** watchdog timer module */
	CSL_CLKRST_MODULE_WDT   =  (1 << 9),
	/** OCP interface module */
	CSL_CLKRST_MODULE_OCPI  =  (1 << 10),
	/** TC module 1 */
	CSL_CLKRST_MODULE_TC1   =  (1 << 11),
	/** TC module 2 */
	CSL_CLKRST_MODULE_TC2   =  (1 << 12),
	/** DSP module */
	CSL_CLKRST_MODULE_DSP   =  (1 << 13)
} CSL_ClkrstModule;


/** @brief Enumeration for CLKRST clocking schemes */
typedef enum {
	/** Fully synchronous clocking scheme */
	CSL_CLKRST_CLKSCHEME_FULLSYNC  =  CSL_CLKRST_ARM_SYSST_CLOCK_SELECT_FULL_SYNC,
	/** Synchronous scalable clocking scheme */
	CSL_CLKRST_CLKSCHEME_SYNCSCAL  =  CSL_CLKRST_ARM_SYSST_CLOCK_SELECT_SYNC_SCAL,
	/** bypass */
	CSL_CLKRST_CLKSCHEME_BYPASS    =  CSL_CLKRST_ARM_SYSST_CLOCK_SELECT_BYPASS,
	/** Mixed mode 3 clocking scheme */
	CSL_CLKRST_CLKSCHEME_MM3       =  CSL_CLKRST_ARM_SYSST_CLOCK_SELECT_MM3,
	/** Mixed mode 4 clocking scheme */
	CSL_CLKRST_CLKSCHEME_MM4       =  CSL_CLKRST_ARM_SYSST_CLOCK_SELECT_MM4
} CSL_ClkrstClkScheme;


/** @brief Enumeration to decide dependence of RESPWR pin on TC's idle entry */
typedef enum {
	/** set RESPWR to logic low when TC enters idle mode */
	CSL_CLKRST_RESPWRTCIDLEENTRY_DEPENDENT    =  CSL_CLKRST_ARM_EWUPCT_REPWR_EN_TC_IDLE_RESPWR_LOW,
	/** do not set RESPWR to logic low when TC enters idle mode */
	CSL_CLKRST_RESPWRTCIDLEENTRY_INDEPENDENT  =  CSL_CLKRST_ARM_EWUPCT_REPWR_EN_TC_IDLE_RESPWR_INACT
}CSL_ClkrstRespwrTcIdlEntry;


/** @brief Enumeration to decide dependence of MPU's idle exit on CHIP_nWKUP pin */
typedef enum {
	/** exit MPU's idle mode if low level on CHIP_nWKUP pin */
	CSL_CLKRST_WKUPCHIPNWKUP_DEPENDENT    =  CSL_CLKRST_ARM_IDLECT1_WKUP_MODE_GATEDON_CHIP_NWKUP,
	/** exit MPU's idle mode regardless of CHIP_nWKUP pin */
	CSL_CLKRST_WKUPCHIPNWKUP_INDEPENDENT  =  CSL_CLKRST_ARM_IDLECT1_WKUP_MODE_INDPTOF_CHIP_NWKUP
}CSL_ClkrstWkupChipNwkup;


/** @brief Enumeration for DSP's idle status */
typedef enum {
	/** DSP megacell is in global-idle state */
	CSL_CLKRST_DSPSTATUS_IDLE    =  CSL_CLKRST_ARM_SYSST_IDLE_DSP_IDLE,
	/** DSP megacell is active */
	CSL_CLKRST_DSPSTATUS_ACTIVE  =  CSL_CLKRST_ARM_SYSST_IDLE_DSP_ACTIVE
} CSL_ClkrstDspStatus;


/** @brief Enumeration for the different reset domains controlled through software */
typedef enum {
	/** MPU megacell */
	CSL_CLKRST_RESETTYPE_MPU      =  (1 << 0),
	/** DSP megacell */
	CSL_CLKRST_RESETTYPE_MGS3     =  (1 << 1),
	/** the API & EMIF interfaces */
	CSL_CLKRST_RESETTYPE_EMIFAPI  =  (1 << 2),
	/** the OMAP gigacell */
	CSL_CLKRST_RESETTYPE_OMAP3    =  (1 << 3),
	/** the MPU peripherals */
	CSL_CLKRST_RESETTYPE_PER      =  (1 << 4)
} CSL_ClkrstResetType;


/** @brief Enumeration for the different sources for reset */
typedef enum {
	/** Power-on reset */
	CSL_CLKRST_RESETSRC_POR    =  CSL_FMKT(CLKRST_ARM_SYSST_POR, YES),
	/** external reset */
	CSL_CLKRST_RESETSRC_EXT    =  CSL_FMKT(CLKRST_ARM_SYSST_EXT_RST, YES),
	/** MPU megacell reset */
	CSL_CLKRST_RESETSRC_MPU    =  CSL_FMKT(CLKRST_ARM_SYSST_ARM_MCRST, YES),
	/** MPU watchdog timer reset */
	CSL_CLKRST_RESETSRC_MPUWD  =  CSL_FMKT(CLKRST_ARM_SYSST_ARM_WDRST, YES),
	/** global software reset */
	CSL_CLKRST_RESETSRC_GLOB   =  CSL_FMKT(CLKRST_ARM_SYSST_GLOB_SWRST, YES),
	/** DSP watchdog timer reset */
	CSL_CLKRST_RESETSRC_DSPWD  =  CSL_FMKT(CLKRST_ARM_SYSST_DSP_WDRST, YES)
} CSL_ClkrstResetSrc;


/** @brief Enumeration for ARM_INTH_CK clock frequency dependence on ARM_CK */
typedef enum {
	/** ARM_INTH_CK clock will be the same as ARM_CK */
	CSL_CLKRST_MPUINTHCK_ARMCK     =  CSL_CLKRST_ARM_CKCTL_ARM_INTHCK_SEL_ARM_CK,
	/** ARM_INTH_CK clock will be half of ARM_CK */
	CSL_CLKRST_MPUINTHCK_ARMCKBY2  =  CSL_CLKRST_ARM_CKCTL_ARM_INTHCK_SEL_ARM_CK_BY2
} CSL_ClkrstMpuInthCk;

/** @brief Enumeration for input clock sources */
typedef enum {
	/** ARM_TIM_CK will be the same as input reference clock */
	CSL_CLKRST_CLKSRC_MPUTIM_IPREFCK      =  CSL_FMKT(CLKRST_ARM_CKCTL_ARM_TIMXO, IP_REF_CK),
	/** ARM_TIM_CK will be the same as CK_GEN1 clock */
	CSL_CLKRST_CLKSRC_MPUTIM_CKGEN1       =  CSL_FMKT(CLKRST_ARM_CKCTL_ARM_TIMXO, CK_GEN1)
} CSL_ClkrstClkSrc;


/** @brief This object contains the reference to the instance of CLKRST opened
 *  using the @a CSL_clkrstOpen().
 *
 *  The pointer to this, is passed to all CLKRST CSL APIs.
 */
typedef struct CSL_ClkrstObj {
	/** This is a pointer to the registers of the instance of CLKRST
     *  referred to by this object
     */
	CSL_ClkrstRegsOvly regs;
	/** This is the instance of CLKRST being referred to by this object  */
	CSL_InstNum  	perNum;
} CSL_ClkrstObj;

typedef struct CSL_ClkrstObj *CSL_ClkrstHandle;

/** @brief This will have the base-address information for the peripheral
 *  instance
 */
typedef struct {
	/** Base-address of the Configuration registers of the peripheral
	 */
	CSL_ClkrstRegsOvly	regs;
} CSL_ClkrstBaseAddress;


/** @brief Module specific parameters. Present implementation doesn't have
 *  any module specific parameters.
 */
typedef struct{
	/** Bit mask to be used for module specific parameters.
         *  The below declaration is just a place-holder for future
 	 *  implementation.
	 */
	CSL_BitMask16   flags;
} CSL_ClkrstParam;

/** @brief Module specific context information. Present implementation doesn't have
 *  any Context information.
 */

typedef struct {
	/** Context information of CLKRST.
         *  The below declaration is just a place-holder for future
 	 *  implementation.
 	 */
    Uint16	contextInfo;
} CSL_ClkrstContext;



/** @brief part of @a CSL_ClkrstHwSetupClkClkScheme used to configure clock dividers
 *
 * This structure is used to configure the clock dividers for the different clocks. The permissible values are 0-3. The clock is divided by 2^(value) */
typedef struct CSL_ClkrstClkDiv {
	/** divider value for TC clock */
	Uint8  tcDiv;
	/** divider value for DSP clock */
	Uint8  dspDiv;
	/** divider value for MPU clock */
	Uint8  mpuDiv;
	/** divider value for peripheral clock */
	Uint8  perDiv;
	/** divider value for LCD clock */
	Uint8  lcdDiv;
	/** divider value for DSP MMU clock */
	Uint8  dspmmuDiv;
} CSL_ClkrstClkDiv;


/** @brief part of @a CSL_ClkrstHwSetupClk used to configure a clocking scheme
 *
 * This structure is used to configure a clock scheme for clkrst including the clock dividers needed in the scheme */
typedef struct CSL_ClkrstHwSetupClkClkScheme {
	/** This member is used to hold the clock scheme information */
	CSL_ClkrstClkScheme  clkScheme;
	/** This instance of @a CSL_ClkrstClkDiv is used to hold information on the clock dividers needed */
	CSL_ClkrstClkDiv     clkDiv;
} CSL_ClkrstHwSetupClkClkScheme;


/** @brief part of @a CSL_ClkrstHwSetupClk used to configure the CLKOUT pins for different domains */
typedef struct CSL_ClkrstHwSetupClkCkout {
	/** TC CLKOUT pin source selection */
	CSL_ClkrstCkoutType  tcDomain;
	/** DSP CLKOUT pin source selection */
	CSL_ClkrstCkoutType  dspDomain;
	/** MPU CLKOUT pin source selection */
	CSL_ClkrstCkoutType  mpuDomain;
} CSL_ClkrstHwSetupClkCkout;


/** @brief part of @a CSL_ClkrstHwSetup used to configure the clock control in CLKRST
 *
 * This structure is used to configure the different clock characteritics in the CLKRST */
typedef struct CSL_ClkrstHwSetupClk {
	/** This pointer to @a CSL_ClkrstHwSetupClkClkScheme is used to configure the clocking scheme of the CLKRST */
	CSL_ClkrstHwSetupClkClkScheme  *clkSchemePtr;
	/** This pointer is used to configure the sources for ARM_TIM_CK clock pin */
	CSL_ClkrstClkSrc               *clkSourcePtr;
	/** This pointer is used to configure the sources for ARM_INTH_CK clock pin */
	CSL_ClkrstMpuInthCk            *mpuInthCkPtr;
	/** This pointer is used to configure the idle entry modes of different clock pins. This takes a bitmask made by bitwise-ORing @a CSL_ClkrstModule except @a CSL_CLKRST_MODULE_DMA & @a CSL_CLKRST_MODULE_LCD */
	Uint16                         *clkIdleEntryPtr;
	/** This pointer is used to configure the CLKOUT pins on different domains */
	CSL_ClkrstHwSetupClkCkout      *ckoutPtr;
} CSL_ClkrstHwSetupClk;


/** @brief part of @a CSL_ClkrstHwSetup used to configure the Power control features of CLKRST
 *
 * This structure configures the dependence of RESPWR on TC's idle mode & the delay between RESPWR going high & clocks starting */
typedef struct CSL_ClkrstHwSetupPwrctl {
	/** This is the delay between the RESPWR going high & the clocks starting */
	Uint8                       delayRespwrActiveToClkStart;
	/** Configures the dependence of RESPWR pin going low when TC goes into idle mode */
	CSL_ClkrstRespwrTcIdlEntry  resPwr;
} CSL_ClkrstHwSetupPwrctl;


/** @brief main structure that is used to setup the CLKRST
 *
 * This structure is used to setup or obtain the existing setup of CLKRST using @a CSL_clkrstHwSetup() & @a CSL_clkrstGetHwSetup() functions respectively. If a particular member pointer is null, then these functions do not setup or get the setup of the corresponding part of CLKRST respectively */
typedef struct CSL_ClkrstHwSetup {
	/** pointer to the structure that contains the information to configure the clock control */
	CSL_ClkrstHwSetupClk     *clkPtr;
	/** pointer to the structure that contains the information to configure power control features */
	CSL_ClkrstHwSetupPwrctl  *pwrctlPtr;
	/** MPU's idle mode exit dependence on CHIP_nWKUP pin */
	CSL_ClkrstWkupChipNwkup  *wkupModePtr;
} CSL_ClkrstHwSetup;


/** @brief used to get the status of CLKRST
 *
 * This structure gets the reset & DSP status of CLKRST module */
typedef struct CSL_ClkrstStatus {
	/** status of the reset source for OMAP Gigacell */
	Uint8                status;
	/** idle mode status of the DSP */
	CSL_ClkrstDspStatus  dspStatus;
} CSL_ClkrstStatus;


/**
 * @brief   The config-structure
 *
 * Used to configure the clkrst using CSL_clkrstHwSetupRaw() function
 */
typedef struct  {
    Uint32 ARM_CKCTL;    /**< ARM clock control register */
    Uint32 ARM_IDLECT1;  /**< ARM idle control register 1 */