cslr_uwire.h

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/** SR1 CS0_FRQ  - field mask */
#define CSL_UWIRE_SR1_CS0_FRQ_MASK       (0x0018u)
/** SR1 CS0_FRQ  - field shift value */
#define CSL_UWIRE_SR1_CS0_FRQ_SHIFT      (0x0003u)
/** SR1 CS0_FRQ  - field reset value */
#define CSL_UWIRE_SR1_CS0_FRQ_RESETVAL   (0x0000u)

/*----CS0_FRQ Tokens----*/
/** SR1 CS0_FRQ  - divide clock by two */
#define CSL_UWIRE_SR1_CS0_FRQ_INTCLKDIV2 (0x0000u)
/** SR1 CS0_FRQ  - divide clock by four */
#define CSL_UWIRE_SR1_CS0_FRQ_INTCLKDIV4 (0x0001u)
/** SR1 CS0_FRQ  - divide clock by eight */
#define CSL_UWIRE_SR1_CS0_FRQ_INTCLKDIV8 (0x0002u)

/** SR1 CS0CS_LVL  - field mask */
#define CSL_UWIRE_SR1_CS0CS_LVL_MASK     (0x0004u)
/** SR1 CS0CS_LVL  - field shift value */
#define CSL_UWIRE_SR1_CS0CS_LVL_SHIFT    (0x0002u)
/** SR1 CS0CS_LVL  - field reset value */
#define CSL_UWIRE_SR1_CS0CS_LVL_RESETVAL (0x0000u)

/*----CS0CS_LVL Tokens----*/
/** SR1 CS0CS_LVL  - active level low */
#define CSL_UWIRE_SR1_CS0CS_LVL_ACTIVELOW (0x0000u)
/** SR1 CS0CS_LVL  - active level high */
#define CSL_UWIRE_SR1_CS0CS_LVL_ACTIVEHIGH (0x0001u)

/** SR1 CS0_EDGE_WR  - field mask */
#define CSL_UWIRE_SR1_CS0_EDGE_WR_MASK   (0x0002u)
/** SR1 CS0_EDGE_WR  - field shift value */
#define CSL_UWIRE_SR1_CS0_EDGE_WR_SHIFT  (0x0001u)
/** SR1 CS0_EDGE_WR  - edge read low */
#define CSL_UWIRE_SR1_CS0_EDGE_WR_LOW    (0x0000u)
/** SR1 CS0_EDGE_WR  - edge read high */
#define CSL_UWIRE_SR1_CS0_EDGE_WR_HIGH (0x0001u)
/** SR1 CS0_EDGE_WR  - field reset value */
#define CSL_UWIRE_SR1_CS0_EDGE_WR_RESETVAL (0x0000u)

/** SR1 CS0_EDGE_RD  - field mask */
#define CSL_UWIRE_SR1_CS0_EDGE_RD_MASK   (0x0001u)
/** SR1 CS0_EDGE_RD  - field shift value */
#define CSL_UWIRE_SR1_CS0_EDGE_RD_SHIFT  (0x0000u)
/** SR1 CS0_EDGE_RD  - edge read low */
#define CSL_UWIRE_SR1_CS0_EDGE_RD_LOW    (0x0000u)
/** SR1 CS0_EDGE_RD  - edge read high */
#define CSL_UWIRE_SR1_CS0_EDGE_RD_HIGH (0x0001u)
/** SR1 CS0_EDGE_RD  - field reset value */
#define CSL_UWIRE_SR1_CS0_EDGE_RD_RESETVAL (0x0000u)

/** SR1  reset value */
#define CSL_UWIRE_SR1_RESETVAL           (0x0000u)

/* SR2 */
/** SR2 CS3_CHK  - field mask */
#define CSL_UWIRE_SR2_CS3_CHK_MASK       (0x0800u)
/** SR2 CS3_CHK  - field shift value */
#define CSL_UWIRE_SR2_CS3_CHK_SHIFT      (0x000Bu)
/** SR2 CS3_CHK  - field reset value */
#define CSL_UWIRE_SR2_CS3_CHK_RESETVAL   (0x0000u)

/*----CS3_CHK Tokens----*/
/** SR2 CS3_CHK  - nocheck for readyness */
#define CSL_UWIRE_SR2_CS3_CHK_NOCHECK    (0x0000u)
/** SR2 CS3_CHK  - check for readyness */
#define CSL_UWIRE_SR2_CS3_CHK_CHECK      (0x0001u)

/** SR2 CS3_FRQ  - field mask */
#define CSL_UWIRE_SR2_CS3_FRQ_MASK       (0x0600u)
/** SR2 CS3_FRQ  - field shift value */
#define CSL_UWIRE_SR2_CS3_FRQ_SHIFT      (0x0009u)
/** SR2 CS3_FRQ  - field reset value */
#define CSL_UWIRE_SR2_CS3_FRQ_RESETVAL   (0x0000u)

/*----CS3_FRQ Tokens----*/
/** SR2 CS3_FRQ  - divide clock by two */
#define CSL_UWIRE_SR2_CS3_FRQ_INTCLKDIV2 (0x0000u)
/** SR2 CS3_FRQ  - divide clock by four */
#define CSL_UWIRE_SR2_CS3_FRQ_INTCLKDIV4 (0x0001u)
/** SR2 CS3_FRQ  - divide clock by eight */
#define CSL_UWIRE_SR2_CS3_FRQ_INTCLKDIV8 (0x0002u)

/** SR2 CS3CS_LVL  - field mask */
#define CSL_UWIRE_SR2_CS3CS_LVL_MASK     (0x0100u)
/** SR2 CS3CS_LVL  - field shift value */
#define CSL_UWIRE_SR2_CS3CS_LVL_SHIFT    (0x0008u)
/** SR2 CS3CS_LVL  - field reset value */
#define CSL_UWIRE_SR2_CS3CS_LVL_RESETVAL (0x0000u)

/*----CS3CS_LVL Tokens----*/
/** SR2 CS3CS_LVL  - active level low */
#define CSL_UWIRE_SR2_CS3CS_LVL_ACTIVELOW (0x0000u)
/** SR2 CS3CS_LVL  - active level high */
#define CSL_UWIRE_SR2_CS3CS_LVL_ACTIVEHIGH (0x0001u)

/** SR2 CS3_EDGE_WR  - field mask */
#define CSL_UWIRE_SR2_CS3_EDGE_WR_MASK   (0x0080u)
/** SR2 CS3_EDGE_WR  - field shift value */
#define CSL_UWIRE_SR2_CS3_EDGE_WR_SHIFT  (0x0007u)
/** SR2 CS3_EDGE_WR  - field reset value */
#define CSL_UWIRE_SR2_CS3_EDGE_WR_RESETVAL (0x0000u)

/** SR2 CS3_EDGE_RD  - field mask */
#define CSL_UWIRE_SR2_CS3_EDGE_RD_MASK   (0x0040u)
/** SR2 CS3_EDGE_RD  - field shift value */
#define CSL_UWIRE_SR2_CS3_EDGE_RD_SHIFT  (0x0006u)
/** SR2 CS3_EDGE_RD  - field reset value */
#define CSL_UWIRE_SR2_CS3_EDGE_RD_RESETVAL (0x0000u)

/** SR2 CS2_CHK  - field mask */
#define CSL_UWIRE_SR2_CS2_CHK_MASK       (0x0020u)
/** SR2 CS2_CHK  - field shift value */
#define CSL_UWIRE_SR2_CS2_CHK_SHIFT      (0x0005u)
/** SR2 CS2_CHK  - field reset value */
#define CSL_UWIRE_SR2_CS2_CHK_RESETVAL   (0x0000u)

/*----CS2_CHK Tokens----*/
/** SR2 CS2_CHK  - nocheck for readyness */
#define CSL_UWIRE_SR2_CS2_CHK_NOCHECK    (0x0000u)
/** SR2 CS2_CHK  - check for readyness */
#define CSL_UWIRE_SR2_CS2_CHK_CHECK      (0x0001u)

/** SR2 CS2_FRQ  - field mask */
#define CSL_UWIRE_SR2_CS2_FRQ_MASK       (0x0018u)
/** SR2 CS2_FRQ  - field shift value */
#define CSL_UWIRE_SR2_CS2_FRQ_SHIFT      (0x0003u)
/** SR2 CS2_FRQ  - field reset value */
#define CSL_UWIRE_SR2_CS2_FRQ_RESETVAL   (0x0000u)

/*----CS2_FRQ Tokens----*/
/** SR2 CS2_FRQ  - divide clock by two */
#define CSL_UWIRE_SR2_CS2_FRQ_INTCLKDIV2 (0x0000u)
/** SR2 CS2_FRQ  - divide clock by four */
#define CSL_UWIRE_SR2_CS2_FRQ_INTCLKDIV4 (0x0001u)
/** SR2 CS2_FRQ  - divide clock by eight */
#define CSL_UWIRE_SR2_CS2_FRQ_INTCLKDIV8 (0x0002u)

/** SR2 CS2CS_LVL  - field mask */
#define CSL_UWIRE_SR2_CS2CS_LVL_MASK     (0x0004u)
/** SR2 CS2CS_LVL  - field shift value */
#define CSL_UWIRE_SR2_CS2CS_LVL_SHIFT    (0x0002u)
/** SR2 CS2CS_LVL  - field reset value */
#define CSL_UWIRE_SR2_CS2CS_LVL_RESETVAL (0x0000u)

/*----CS2CS_LVL Tokens----*/
/** SR2 CS2CS_LVL  - active level low */
#define CSL_UWIRE_SR2_CS2CS_LVL_ACTIVELOW (0x0000u)
/** SR2 CS2CS_LVL  - active level high */
#define CSL_UWIRE_SR2_CS2CS_LVL_ACTIVEHIGH (0x0001u)

/** SR2 CS2_EDGE_WR  - field mask */
#define CSL_UWIRE_SR2_CS2_EDGE_WR_MASK   (0x0002u)
/** SR2 CS2_EDGE_WR  - field shift value */
#define CSL_UWIRE_SR2_CS2_EDGE_WR_SHIFT  (0x0001u)
/** SR2 CS2_EDGE_WR  - field reset value */
#define CSL_UWIRE_SR2_CS2_EDGE_WR_RESETVAL (0x0000u)

/** SR2 CS2_EDGE_RD  - field mask */
#define CSL_UWIRE_SR2_CS2_EDGE_RD_MASK   (0x0001u)
/** SR2 CS2_EDGE_RD  - field shift value */
#define CSL_UWIRE_SR2_CS2_EDGE_RD_SHIFT  (0x0000u)
/** SR2 CS2_EDGE_RD  - field reset value */
#define CSL_UWIRE_SR2_CS2_EDGE_RD_RESETVAL (0x0000u)

/** SR2 - reset value */
#define CSL_UWIRE_SR2_RESETVAL           (0x0000u)

/* SR3 */
/** SR3 CK_FREQ  - field mask */
#define CSL_UWIRE_SR3_CK_FREQ_MASK       (0x0006u)
/** SR3 CK_FREQ  - field shift value */
#define CSL_UWIRE_SR3_CK_FREQ_SHIFT      (0x0001u)
/** SR3 CK_FREQ  - field reset value */
#define CSL_UWIRE_SR3_CK_FREQ_RESETVAL   (0x0000u)

/*----CK_FREQ Tokens----*/
/** SR3 CK_FRQ  - divide external clock by two */
#define CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV2 (0x0000u)
/** SR3 CK_FRQ  - divide external clock by four */
#define CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV4 (0x0001u)
/** SR3 CK_FRQ  - divide external clock by seven */
#define CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV7 (0x0002u)
/** SR3 CK_FRQ  - divide external clock by ten */
#define CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV10 (0x0003u)

/** SR3 CLK_EN  - field mask */
#define CSL_UWIRE_SR3_CLK_EN_MASK        (0x0001u)
/** SR3 CLK_EN  - field shift value */
#define CSL_UWIRE_SR3_CLK_EN_SHIFT       (0x0000u)
/** SR3 CLK_EN  - field reset value */
#define CSL_UWIRE_SR3_CLK_EN_RESETVAL    (0x0000u)

/*----CLK_EN Tokens----*/
/** SR3 CLK_EN  - clock disable */
#define CSL_UWIRE_SR3_CLK_EN_DISABLE     (0x0000u)
/** SR3 CLK_EN  - clock enable */
#define CSL_UWIRE_SR3_CLK_EN_ENABLE      (0x0001u)

/** SR3  reset value */
#define CSL_UWIRE_SR3_RESETVAL           (0x0000u)

/* SR4 */
/** SR4 CLK_IN  - field mask */
#define CSL_UWIRE_SR4_CLK_IN_MASK        (0x0001u)
/** SR4 CLK_IN  - field shift value */
#define CSL_UWIRE_SR4_CLK_IN_SHIFT       (0x0000u)
/** SR4 CLK_IN  - field reset value */
#define CSL_UWIRE_SR4_CLK_IN_RESETVAL    (0x0000u)

/*----CLK_IN Tokens----*/
/** SR4 CLK_IN  - clock noninverted */
#define CSL_UWIRE_SR4_CLK_IN_NONINVERTED (0x0000u)
/** SR4 CLK_IN  - clock inverted */
#define CSL_UWIRE_SR4_CLK_IN_INVERTED    (0x0001u)

/** SR4  reset value */
#define CSL_UWIRE_SR4_RESETVAL           (0x0000u)

/* SR5 */
/** SR5 CS_TOGGLE_TX_EN  - field mask */
#define CSL_UWIRE_SR5_CS_TOGGLE_TX_EN_MASK (0x0008u)
/** SR5 CS_TOGGLE_TX_EN  - field shift value */
#define CSL_UWIRE_SR5_CS_TOGGLE_TX_EN_SHIFT (0x0003u)
/** SR5 CS_TOGGLE_TX_EN  - field reset value */
#define CSL_UWIRE_SR5_CS_TOGGLE_TX_EN_RESETVAL (0x0000u)

/*----CS_TOGGLE_TX_EN Tokens----*/
/** SR5 CS_TOGGLE_TX_EN  - disable cs toggle */
#define CSL_UWIRE_SR5_CS_TOGGLE_TX_EN_DISABLE (0x0000u)
/** SR5 CS_TOGGLE_TX_EN  - enable cs toggle */
#define CSL_UWIRE_SR5_CS_TOGGLE_TX_EN_ENABLE (0x0001u)

/** SR5 AUTO_TX_EN  - field mask */
#define CSL_UWIRE_SR5_AUTO_TX_EN_MASK    (0x0004u)
/** SR5 AUTO_TX_EN  - field shift value */
#define CSL_UWIRE_SR5_AUTO_TX_EN_SHIFT   (0x0002u)
/** SR5 AUTO_TX_EN  - field reset value */
#define CSL_UWIRE_SR5_AUTO_TX_EN_RESETVAL (0x0000u)

/*----AUTO_TX_EN Tokens----*/
/** SR5 AUTO_TX_EN  - disable auto transmit */
#define CSL_UWIRE_SR5_AUTO_TX_EN_DISABLE (0x0000u)
/** SR5 AUTO_TX_EN  - enable auto transmit */
#define CSL_UWIRE_SR5_AUTO_TX_EN_ENABLE  (0x0001u)

/** SR5 IT_EN  - field mask */
#define CSL_UWIRE_SR5_IT_EN_MASK         (0x0002u)
/** SR5 IT_EN  - field shift value */
#define CSL_UWIRE_SR5_IT_EN_SHIFT        (0x0001u)
/** SR5 IT_EN  - field reset value */
#define CSL_UWIRE_SR5_IT_EN_RESETVAL     (0x0000u)

/*----IT_EN Tokens----*/
/** SR5 IT_EN  - disable interrupt */
#define CSL_UWIRE_SR5_IT_EN_DISABLE      (0x0000u)
/** SR5 IT_EN  - enable interrupt */
#define CSL_UWIRE_SR5_IT_EN_ENABLE       (0x0001u)

/** SR5 DMA_TX_EN  - field mask */
#define CSL_UWIRE_SR5_DMA_TX_EN_MASK     (0x0001u)
/** SR5 DMA_TX_EN  - field shift value */
#define CSL_UWIRE_SR5_DMA_TX_EN_SHIFT    (0x0000u)
/** SR5 DMA_TX_EN  - field reset value */
#define CSL_UWIRE_SR5_DMA_TX_EN_RESETVAL (0x0000u)

/*----DMA_TX_EN Tokens----*/
/** SR5 DMA_TX_EN  - disable DMA */
#define CSL_UWIRE_SR5_DMA_TX_EN_DISABLE  (0x0000u)
/** SR5 DMA_TX_EN  - enable DMA */
#define CSL_UWIRE_SR5_DMA_TX_EN_ENABLE   (0x0001u)

/** SR5 reset value */
#define CSL_UWIRE_SR5_RESETVAL           (0x0000u)

#endif /* _CSLR_UWIRE_001_H_ */

#endif /* _CSLR_UWIRE_H_ */