cslr_uwire.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 558 行 · 第 1/2 页

/** ============================================================================
 *   @file  cslr_uwire.h
 *
 *   @path  $(CSLPATH)\arm\uwire\src
 *
 *   @desc  Register layer API file for MicroWire CSL
 *
 */
 
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/* =============================================================================
 *  Revision History
 *  ================
 *  23-Jun-2004 rr  File created
 *
 * =============================================================================
 */
 
#ifndef _CSLR_UWIRE_H_
#define _CSLR_UWIRE_H_

#ifndef _CSLR_UWIRE_001_H_
#define _CSLR_UWIRE_001_H_
/*********************************************************************
 * 
 * \brief This file contains the Register Desciptions for UWIRE
 * 
 *********************************************************************/

#include <cslr.h>
#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {

    /** transmit/receive data register */
    volatile Uint16 TDR_RDR;
    /** */
    volatile Uint8 RSVD0[2];
    /** control and status register */
    volatile Uint16 CSR;
    /** */
    volatile Uint8 RSVD1[2];
    /** setup register1 */
    volatile Uint16 SR1;
    /** */
    volatile Uint8 RSVD2[2];
    /** setup register2 */
    volatile Uint16 SR2;
    /** */
    volatile Uint8 RSVD3[2];
    /** setup register3 */
    volatile Uint16 SR3;
    /** */
    volatile Uint8 RSVD4[2];
    /** setup register4 */
    volatile Uint16 SR4;
    /** */
    volatile Uint8 RSVD5[2];
    /** setup register5 */
    volatile Uint16 SR5;
    
} CSL_UwireRegs;

/**
 * Overlay structure typedef definition
 */
typedef volatile CSL_UwireRegs * CSL_UwireRegsOvly;


/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* TDR_RDR */
/** TDR_RDR TDR_RDR - field mask */
#define CSL_UWIRE_TDR_RDR_TDR_RDR_MASK   (0xFFFFu)
/** TDR_RDR TDR_RDR - field shift value */
#define CSL_UWIRE_TDR_RDR_TDR_RDR_SHIFT  (0x0000u)
/** TDR_RDR TDR_RDR - field reset value */
#define CSL_UWIRE_TDR_RDR_TDR_RDR_RESETVAL (0x0000u)

/** TDR_RDR reset value */
#define CSL_UWIRE_TDR_RDR_RESETVAL       (0x0000u)

/* TDR */
/** TDR TD - field mask */
#define CSL_UWIRE_TDR_TD_MASK            (0xFFFFu)
/** TDR TD - field shift value */
#define CSL_UWIRE_TDR_TD_SHIFT           (0x0000u)
/** TDR TD - field reset value */
#define CSL_UWIRE_TDR_TD_RESETVAL        (0x0000u)

/** TDR reset value */
#define CSL_UWIRE_TDR_RESETVAL           (0x0000u)

/* RDR */

/** RDR RD - field mask */
#define CSL_UWIRE_RDR_RD_MASK            (0xFFFFu)
/** RDR RD - field shift value */
#define CSL_UWIRE_RDR_RD_SHIFT           (0x0000u)
/** RDR RD - field reset value */
#define CSL_UWIRE_RDR_RD_RESETVAL        (0x0000u)

/** RDR reset value */
#define CSL_UWIRE_RDR_RESETVAL           (0x0000u)

/* CSR */

/** CSR RDRB - field mask */
#define CSL_UWIRE_CSR_RDRB_MASK          (0x8000u)
/** CSR RDRB - field shift value */
#define CSL_UWIRE_CSR_RDRB_SHIFT         (0x000Fu)
/** CSR RDRB - field reset value */
#define CSL_UWIRE_CSR_RDRB_RESETVAL      (0x0000u)

/*----RDRB Tokens----*/
/** CSR RDRB - RDR is empty */
#define CSL_UWIRE_CSR_RDRB_EMPTY         (0x0000u)
/** CSR RDRB - RDR is full*/
#define CSL_UWIRE_CSR_RDRB_FULL          (0x0001u)

/** CSR CSRB - field mask */
#define CSL_UWIRE_CSR_CSRB_MASK          (0x4000u)
/** CSR CSRB - field shift value */
#define CSL_UWIRE_CSR_CSRB_SHIFT         (0x000Eu)
/** CSR CSRB - field reset value */
#define CSL_UWIRE_CSR_CSRB_RESETVAL      (0x0000u)

/*----CSRB Tokens----*/

/** CSR CSRB - CSR is ready */
#define CSL_UWIRE_CSR_CSRB_READY         (0x0000u)
/** CSR CSRB - CSR is  not ready */
#define CSL_UWIRE_CSR_CSRB_NOTREADY      (0x0001u)

/** CSR START - field mask */
#define CSL_UWIRE_CSR_START_MASK         (0x2000u)
/** CSR START - field shift value */
#define CSL_UWIRE_CSR_START_SHIFT        (0x000Du)
/** CSR START - field reset value */
#define CSL_UWIRE_CSR_START_RESETVAL     (0x0000u)

/*----START Tokens----*/
/** CSR START - start disable */
#define CSL_UWIRE_CSR_START_DISABLE      (0x0000u)
/** CSR START - start enable */
#define CSL_UWIRE_CSR_START_ENABLE       (0x0001u)

/** CSR  - field mask */
/** CSR CS_CMD - field mask */
#define CSL_UWIRE_CSR_CS_CMD_MASK        (0x1000u)
/** CSR CS_CMD - field shift value */
#define CSL_UWIRE_CSR_CS_CMD_SHIFT       (0x000Cu)
/** CSR CS_CMD - field reset value */
#define CSL_UWIRE_CSR_CS_CMD_RESETVAL    (0x0000u)

/*----CS_CMD Tokens----*/
/** CSR CS_CMD - chip select is inactive */
#define CSL_UWIRE_CSR_CS_CMD_INACTIVE    (0x0000u)
/** CSR CS_CMD - chip select is active */
#define CSL_UWIRE_CSR_CS_CMD_ACTIVE      (0x0001u)

/** CSR INDEX - field mask */
#define CSL_UWIRE_CSR_INDEX_MASK         (0x0C00u)
/** CSR INDEX - field shift value */
#define CSL_UWIRE_CSR_INDEX_SHIFT        (0x000Au)
/** CSR INDEX - field reset value */
#define CSL_UWIRE_CSR_INDEX_RESETVAL     (0x0000u)

/*----INDEX Tokens----*/
/** CSR INDEX - slect CS0 */
#define CSL_UWIRE_CSR_INDEX_CS0          (0x0000u)
/** CSR INDEX - slect CS1 */
#define CSL_UWIRE_CSR_INDEX_CS1          (0x0001u)
/** CSR INDEX - slect CS2 */
#define CSL_UWIRE_CSR_INDEX_CS2          (0x0002u)
/** CSR INDEX - slect CS3 */
#define CSL_UWIRE_CSR_INDEX_CS3          (0x0003u)

/** CSR  - field mask */
/** CSR NB_BITS_WR - field mask */
#define CSL_UWIRE_CSR_NB_BITS_WR_MASK    (0x03E0u)
/** CSR NB_BITS_WR - field shift value */
#define CSL_UWIRE_CSR_NB_BITS_WR_SHIFT   (0x0005u)
/** CSR NB_BITS_WR - field reset value */
#define CSL_UWIRE_CSR_NB_BITS_WR_RESETVAL (0x0000u)

/** CSR  - field mask */
/** CSR NB_BITS_RD - field mask */
#define CSL_UWIRE_CSR_NB_BITS_RD_MASK    (0x001Fu)
/** CSR NB_BITS_RD - field shift value */
#define CSL_UWIRE_CSR_NB_BITS_RD_SHIFT   (0x0000u)
/** CSR NB_BITS_RD - field reset value */
#define CSL_UWIRE_CSR_NB_BITS_RD_RESETVAL (0x0000u)

/** CSR register reset value */
#define CSL_UWIRE_CSR_RESETVAL           (0x0000u)

/* SR1 */

/** SR1 CS1_CHK  - field mask */
#define CSL_UWIRE_SR1_CS1_CHK_MASK       (0x0800u)
/** SR1 CS1_CHK  - field shift value */
#define CSL_UWIRE_SR1_CS1_CHK_SHIFT      (0x000Bu)
/** SR1 CS1_CHK  - field reset value */
#define CSL_UWIRE_SR1_CS1_CHK_RESETVAL   (0x0000u)

/*----CS1_CHK Tokens----*/
/** SR1 CS1_CHK  - nocheck for readyness */
#define CSL_UWIRE_SR1_CS1_CHK_NOCHECK    (0x0000u)
/** SR1 CS1_CHK  - check for readyness */
#define CSL_UWIRE_SR1_CS1_CHK_CHECK      (0x0001u)

/** SR1 CS1_FRQ  - field mask */
#define CSL_UWIRE_SR1_CS1_FRQ_MASK       (0x0600u)
/** SR1 CS1_FRQ  - field shift value */
#define CSL_UWIRE_SR1_CS1_FRQ_SHIFT      (0x0009u)
/** SR1 CS1_FRQ  - field reset value */
#define CSL_UWIRE_SR1_CS1_FRQ_RESETVAL   (0x0000u)

/*----CS1_FRQ Tokens----*/
/** SR1 CS1_FRQ  - divide clock by two */
#define CSL_UWIRE_SR1_CS1_FRQ_INTCLKDIV2 (0x0000u)
/** SR1 CS1_FRQ  - divide clock by four */
#define CSL_UWIRE_SR1_CS1_FRQ_INTCLKDIV4 (0x0001u)
/** SR1 CS1_FRQ  - divide clock by eight */
#define CSL_UWIRE_SR1_CS1_FRQ_INTCLKDIV8 (0x0002u)

/** SR1 CS1CS_LVL  - field mask */
#define CSL_UWIRE_SR1_CS1CS_LVL_MASK     (0x0100u)
/** SR1 CS1CS_LVL  - field shift value */
#define CSL_UWIRE_SR1_CS1CS_LVL_SHIFT    (0x0008u)
/** SR1 CS1CS_LVL  - field reset value */
#define CSL_UWIRE_SR1_CS1CS_LVL_RESETVAL (0x0000u)

/*----CS1CS_LVL Tokens----*/
/** SR1 CS1CS_LVL  - active level low */
#define CSL_UWIRE_SR1_CS1CS_LVL_ACTIVELOW (0x0000u)
/** SR1 CS1CS_LVL  - active level high */
#define CSL_UWIRE_SR1_CS1CS_LVL_ACTIVEHIGH (0x0001u)

/** SR1 CS1_EDGE_WR  - field mask */
#define CSL_UWIRE_SR1_CS1_EDGE_WR_MASK   (0x0080u)
/** SR1 CS1_EDGE_WR  - field shift value */
#define CSL_UWIRE_SR1_CS1_EDGE_WR_SHIFT  (0x0007u)
/** SR1 CS1_EDGE_WR  - field reset value */
#define CSL_UWIRE_SR1_CS1_EDGE_WR_RESETVAL (0x0000u)

/** SR1 CS1_EDGE_RD  - field mask */
#define CSL_UWIRE_SR1_CS1_EDGE_RD_MASK   (0x0040u)
/** SR1 CS1_EDGE_RD  - field shift value */
#define CSL_UWIRE_SR1_CS1_EDGE_RD_SHIFT  (0x0006u)
/** SR1 CS1_EDGE_RD  - field reset value */
#define CSL_UWIRE_SR1_CS1_EDGE_RD_RESETVAL (0x0000u)

/** SR1 CS0_CHK  - field mask */
#define CSL_UWIRE_SR1_CS0_CHK_MASK       (0x0020u)
/** SR1 CS0_CHK  - field shift value */
#define CSL_UWIRE_SR1_CS0_CHK_SHIFT      (0x0005u)
/** SR1 CS0_CHK  - field reset value */
#define CSL_UWIRE_SR1_CS0_CHK_RESETVAL   (0x0000u)

/*----CS0_CHK Tokens----*/
/** SR1 CS0_CHK  - nocheck for readyness */
#define CSL_UWIRE_SR1_CS0_CHK_NOCHECK    (0x0000u)
/** SR1 CS0_CHK  - check for readyness */
#define CSL_UWIRE_SR1_CS0_CHK_CHECK      (0x0001u)