cslr_dspmmu.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 419 行

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/** ============================================================================ *   @file  cslr_dspmmu_001.h * *   @path  $(CSLPATH)\dsp\dspmmu\src * *   @desc  Register layer header file for the DSP MMU CSL * */ /* ============================================================================ *   Copyright (c) Texas Instruments Inc 2002, 2003 * *   Use of this software is controlled by the terms and conditions found in *   the license agreement under which this software has been supplied *   priovided *  ============================================================================ *//* ============================================================================= *  Revision History *  ================ *  16-Apr-2004 anj File Created. *	04-Feb-2005 sd	Changes for the bug fix *	23-Feb-2005 sd	Changes for the bug fix * ============================================================================= */#ifndef _CSLR_DSPMMU_001_H_#define _CSLR_DSPMMU_001_H_#include <cslr.h>#include <tistdtypes.h>/* *  Register Overlay Structure */typedef struct  {    volatile Uint32 PREFETCH_REG;    volatile Uint32 WALKING_ST_REG;    volatile Uint32 CNTL_REG;    volatile Uint32 FAULT_AD_H_REG;    volatile Uint32 FAULT_AD_L_REG;    volatile Uint32 FAULT_ST_REG;    volatile Uint32 IT_ACK_REG;    volatile Uint32 TTB_H_REG;    volatile Uint32 TTB_L_REG;    volatile Uint32 LOCK_REG;    volatile Uint32 LD_TLB_REG;    volatile Uint32 CAM_H_REG;    volatile Uint32 CAM_L_REG;    volatile Uint32 RAM_H_REG;    volatile Uint16 RAM_L_REG;    const char RSVD0[2];    volatile Uint32 GFLUSH_REG;    volatile Uint32 FLUSH_ENTRY_REG;    volatile Uint32 READ_CAM_H_REG;    volatile Uint32 READ_CAM_L_REG;    volatile Uint32 READ_RAM_H_REG;    volatile Uint32 READ_RAM_L_REG;    volatile Uint32 DSPMMU_IDLE_CTRL;} CSL_DspmmuRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_DspmmuRegs * CSL_DspmmuRegsOvly;/* *  Register Id's */typedef enum  {   CSL_DSPMMU_PREFETCH_REG = 0x0000u,   CSL_DSPMMU_WALKING_ST_REG = 0x0004u,   CSL_DSPMMU_CNTL_REG = 0x0008u,   CSL_DSPMMU_FAULT_AD_H_REG = 0x000cu,   CSL_DSPMMU_FAULT_AD_L_REG = 0x0010u,   CSL_DSPMMU_FAULT_ST_REG = 0x0014u,   CSL_DSPMMU_IT_ACK_REG = 0x0018u,   CSL_DSPMMU_TTB_H_REG = 0x001cu,   CSL_DSPMMU_TTB_L_REG = 0x0020u,   CSL_DSPMMU_LOCK_REG = 0x0024u,   CSL_DSPMMU_LD_TLB_REG = 0x0028u,   CSL_DSPMMU_CAM_H_REG = 0x002cu,   CSL_DSPMMU_CAM_L_REG = 0x0030u,   CSL_DSPMMU_RAM_H_REG = 0x0034u,   CSL_DSPMMU_RAM_L_REG = 0x0038u,   CSL_DSPMMU_GFLUSH_REG = 0x003cu,   CSL_DSPMMU_FLUSH_ENTRY_REG = 0x0040u,   CSL_DSPMMU_READ_CAM_H_REG = 0x0044u,   CSL_DSPMMU_READ_CAM_L_REG = 0x0048u,   CSL_DSPMMU_READ_RAM_H_REG = 0x004cu,   CSL_DSPMMU_READ_RAM_L_REG = 0x0050u,   CSL_DSPMMU_DSPMMU_IDLE_CTRL = 0x0054u} CSL_DspMmuRegIds;/** * Field Definition Macros *//** *  PREFETCH_REG */#define CSL_DSPMMU_PREFETCH_REG_PREFADDR_MASK (0x00003FFFu)#define CSL_DSPMMU_PREFETCH_REG_PREFADDR_SHIFT (0x00000000u)#define CSL_DSPMMU_PREFETCH_REG_PREFADDR_RESETVAL (0x00000000u)#define CSL_DSPMMU_PREFETCH_REG_RESETVAL (0x00000000u)/** *  WALKING_ST_REG */#define CSL_DSPMMU_WALKING_ST_REG_WALK_WORKING_MASK (0x00000002u)#define CSL_DSPMMU_WALKING_ST_REG_WALK_WORKING_SHIFT (0x00000001u)#define CSL_DSPMMU_WALKING_ST_REG_WALK_WORKING_RESETVAL (0x00000000u)#define CSL_DSPMMU_WALKING_ST_REG_PREFETCH_ON_MASK (0x00000001u)#define CSL_DSPMMU_WALKING_ST_REG_PREFETCH_ON_SHIFT (0x00000000u)#define CSL_DSPMMU_WALKING_ST_REG_PREFETCH_ON_RESETVAL (0x00000000u)#define CSL_DSPMMU_WALKING_ST_REG_RESETVAL (0x00000000u)/** *  CNTL_REG */#define CSL_DSPMMU_CNTL_REG_WTL_EN_MASK  (0x00000004u)#define CSL_DSPMMU_CNTL_REG_WTL_EN_SHIFT (0x00000002u)#define CSL_DSPMMU_CNTL_REG_WTL_EN_RESETVAL (0x00000000u)#define CSL_DSPMMU_CNTL_REG_WTL_EN_DISABLE (0x00000000u)#define CSL_DSPMMU_CNTL_REG_WTL_EN_ENABLE (0x00000001u)#define CSL_DSPMMU_CNTL_REG_MMU_EN_MASK  (0x00000002u)#define CSL_DSPMMU_CNTL_REG_MMU_EN_SHIFT (0x00000001u)#define CSL_DSPMMU_CNTL_REG_MMU_EN_RESETVAL (0x00000000u)#define CSL_DSPMMU_CNTL_REG_MMU_EN_DISABLE (0x00000000u)#define CSL_DSPMMU_CNTL_REG_MMU_EN_ENABLE (0x00000001u)#define CSL_DSPMMU_CNTL_REG_RESET_SW_MASK (0x00000001u)#define CSL_DSPMMU_CNTL_REG_RESET_SW_SHIFT (0x00000000u)#define CSL_DSPMMU_CNTL_REG_RESET_SW_RESETVAL (0x00000000u)#define CSL_DSPMMU_CNTL_REG_RESET_SW_RESET (0x00000000u)#define CSL_DSPMMU_CNTL_REG_RESETVAL     (0x00000000u)/** *  FAULT_AD_H_REG */#define CSL_DSPMMU_FAULT_AD_H_REG_FAULT_ADDRESS_MSB_MASK (0x000000FFu)#define CSL_DSPMMU_FAULT_AD_H_REG_FAULT_ADDRESS_MSB_SHIFT (0x00000000u)#define CSL_DSPMMU_FAULT_AD_H_REG_FAULT_ADDRESS_MSB_RESETVAL (0x00000000u)#define CSL_DSPMMU_FAULT_AD_H_REG_RESETVAL (0x00000000u)/** * FAULT_AD_L_REG */#define CSL_DSPMMU_FAULT_AD_L_REG_FAULT_ADDRESS_LSB_MASK (0x0000FFFFu)#define CSL_DSPMMU_FAULT_AD_L_REG_FAULT_ADDRESS_LSB_SHIFT (0x00000000u)#define CSL_DSPMMU_FAULT_AD_L_REG_FAULT_ADDRESS_LSB_RESETVAL (0x00000000u)#define CSL_DSPMMU_FAULT_AD_L_REG_RESETVAL (0x00000000u)/** *  FAULT_ST_REG */#define CSL_DSPMMU_FAULT_ST_REG_PREFETCH_ERR_MASK (0x00000008u)#define CSL_DSPMMU_FAULT_ST_REG_PREFETCH_ERR_SHIFT (0x00000003u)#define CSL_DSPMMU_FAULT_ST_REG_PREFETCH_ERR_RESETVAL (0x00000000u)#define CSL_DSPMMU_FAULT_ST_REG_PERM_FAULT_MASK (0x00000004u)#define CSL_DSPMMU_FAULT_ST_REG_PERM_FAULT_SHIFT (0x00000002u)#define CSL_DSPMMU_FAULT_ST_REG_PERM_FAULT_RESETVAL (0x00000000u)#define CSL_DSPMMU_FAULT_ST_REG_TLB_MISS_MASK (0x00000002u)#define CSL_DSPMMU_FAULT_ST_REG_TLB_MISS_SHIFT (0x00000001u)#define CSL_DSPMMU_FAULT_ST_REG_TLB_MISS_RESETVAL (0x00000000u)#define CSL_DSPMMU_FAULT_ST_REG_TRANS_FAULT_MASK (0x00000001u)#define CSL_DSPMMU_FAULT_ST_REG_TRANS_FAULT_SHIFT (0x00000000u)#define CSL_DSPMMU_FAULT_ST_REG_TRANS_FAULT_RESETVAL (0x00000000u)#define CSL_DSPMMU_FAULT_ST_REG_RESETVAL (0x00000000u)/** *  IT_ACK_REG */#define CSL_DSPMMU_IT_ACK_REG_IT_ACK_MASK (0x00000001u)#define CSL_DSPMMU_IT_ACK_REG_IT_ACK_SHIFT (0x00000000u)#define CSL_DSPMMU_IT_ACK_REG_IT_ACK_RESETVAL (0x00000000u)#define CSL_DSPMMU_IT_ACK_REG_RESETVAL   (0x00000000u)/** *  TTB_H_REG */#define CSL_DSPMMU_TTB_H_REG_TTB_H_REG_MASK (0x0000FFFFu)#define CSL_DSPMMU_TTB_H_REG_TTB_H_REG_SHIFT (0x00000000u)#define CSL_DSPMMU_TTB_H_REG_TTB_H_REG_RESETVAL (0x00000000u)#define CSL_DSPMMU_TTB_H_REG_RESETVAL    (0x00000000u)/** *  TTB_L_REG */#define CSL_DSPMMU_TTB_L_REG_TTB_L_REG_MASK (0x0000FF80u)#define CSL_DSPMMU_TTB_L_REG_TTB_L_REG_SHIFT (0x00000007u)#define CSL_DSPMMU_TTB_L_REG_TTB_L_REG_RESETVAL (0x00000000u)#define CSL_DSPMMU_TTB_L_REG_RESETVAL    (0x00000000u)/** *  LOCK_REG */#define CSL_DSPMMU_LOCK_REG_BASE_VALUE_MASK (0x0000FC00u)#define CSL_DSPMMU_LOCK_REG_BASE_VALUE_SHIFT (0x0000000Au)#define CSL_DSPMMU_LOCK_REG_BASE_VALUE_RESETVAL (0x00000000u)#define CSL_DSPMMU_LOCK_REG_CURRENT_VICTIM_MASK (0x000003F0u)#define CSL_DSPMMU_LOCK_REG_CURRENT_VICTIM_SHIFT (0x00000004u)#define CSL_DSPMMU_LOCK_REG_CURRENT_VICTIM_RESETVAL (0x00000000u)#define CSL_DSPMMU_LOCK_REG_RESETVAL     (0x00000000u)/** *  LD_TLB_REG */#define CSL_DSPMMU_LD_TLB_REG_LD_TLB_ITEM_MASK (0x00000001u)#define CSL_DSPMMU_LD_TLB_REG_LD_TLB_ITEM_SHIFT (0x00000000u)#define CSL_DSPMMU_LD_TLB_REG_LD_TLB_ITEM_RESETVAL (0x00000000u)#define CSL_DSPMMU_LD_TLB_REG_LD_TLB_ITEM_LOAD (0x00000001u)#define CSL_DSPMMU_LD_TLB_REG_READ_TLB_ITEM_MASK (0x00000002u)#define CSL_DSPMMU_LD_TLB_REG_READ_TLB_ITEM_SHIFT (0x00000001u)#define CSL_DSPMMU_LD_TLB_REG_READ_TLB_ITEM_RESETVAL (0x00000000u)#define CSL_DSPMMU_LD_TLB_REG_READ_TLB_ITEM_READ (0x00000001u)#define CSL_DSPMMU_LD_TLB_REG_RESETVAL   (0x00000000u)/** *  CAM_H_REG */#define CSL_DSPMMU_CAM_H_REG_VA_TAG_L1_H_MASK (0x0000FFFFu)#define CSL_DSPMMU_CAM_H_REG_VA_TAG_L1_H_SHIFT (0x00000000u)#define CSL_DSPMMU_CAM_H_REG_VA_TAG_L1_H_RESETVAL (0x00000000u)#define CSL_DSPMMU_CAM_H_REG_RESETVAL    (0x00000000u)/** *  CAM_L_REG */#define CSL_DSPMMU_CAM_L_REG_VA_TAG_L1_L_MASK (0x0000C000u)#define CSL_DSPMMU_CAM_L_REG_VA_TAG_L1_L_SHIFT (0x0000000Eu)#define CSL_DSPMMU_CAM_L_REG_VA_TAG_L1_L_RESETVAL (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_VA_TAG_L2_MASK (0x00003FF0u)#define CSL_DSPMMU_CAM_L_REG_VA_TAG_L2_SHIFT (0x00000004u)#define CSL_DSPMMU_CAM_L_REG_VA_TAG_L2_RESETVAL (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_P_MASK      (0x00000008u)#define CSL_DSPMMU_CAM_L_REG_P_SHIFT     (0x00000003u)#define CSL_DSPMMU_CAM_L_REG_P_RESETVAL  (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_P_PRESERVE  (0x00000001u)#define CSL_DSPMMU_CAM_L_REG_V_MASK      (0x00000004u)#define CSL_DSPMMU_CAM_L_REG_V_SHIFT     (0x00000002u)#define CSL_DSPMMU_CAM_L_REG_V_RESETVAL  (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_SLST_MASK   (0x00000003u)#define CSL_DSPMMU_CAM_L_REG_SLST_SHIFT  (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_SLST_RESETVAL (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_SLST_SECTION (0x00000000u)#define CSL_DSPMMU_CAM_L_REG_SLST_LARGE  (0x00000001u)#define CSL_DSPMMU_CAM_L_REG_SLST_SMALL  (0x00000002u)#define CSL_DSPMMU_CAM_L_REG_SLST_TINY   (0x00000003u)#define CSL_DSPMMU_CAM_L_REG_RESETVAL    (0x00000000u)/** *  RAM_H_REG */#define CSL_DSPMMU_RAM_H_REG_RAM_MSB_MASK (0x0000FFFFu)#define CSL_DSPMMU_RAM_H_REG_RAM_MSB_SHIFT (0x00000000u)#define CSL_DSPMMU_RAM_H_REG_RAM_MSB_RESETVAL (0x00000000u)#define CSL_DSPMMU_RAM_H_REG_RESETVAL    (0x00000000u)/** *  RAM_L_REG */#define CSL_DSPMMU_RAM_L_REG_RAM_LSB_MASK (0x0000FC00u)#define CSL_DSPMMU_RAM_L_REG_RAM_LSB_SHIFT (0x0000000Au)#define CSL_DSPMMU_RAM_L_REG_RAM_LSB_RESETVAL (0x00000000u)#define CSL_DSPMMU_RAM_L_REG_AP_MASK     (0x00000300u)#define CSL_DSPMMU_RAM_L_REG_AP_SHIFT    (0x00000008u)#define CSL_DSPMMU_RAM_L_REG_AP_RESETVAL (0x00000000u)#define CSL_DSPMMU_RAM_L_REG_AP_NOACCESS (0x00000000u)/*#define CSL_DSPMMU_RAM_L_REG_AP_NOACCESS (0x00000001u)*/#define CSL_DSPMMU_RAM_L_REG_AP_READONLY (0x00000002u)#define CSL_DSPMMU_RAM_L_REG_AP_FULLACCESS (0x00000003u)#define CSL_DSPMMU_RAM_L_REG_RESETVAL    (0x00000000u)/** *  GFLUSH_REG */#define CSL_DSPMMU_GFLUSH_REG_GLOBAL_FLUSH_MASK (0x00000001u)#define CSL_DSPMMU_GFLUSH_REG_GLOBAL_FLUSH_SHIFT (0x00000000u)#define CSL_DSPMMU_GFLUSH_REG_GLOBAL_FLUSH_RESETVAL (0x00000000u)#define CSL_DSPMMU_GFLUSH_REG_GLOBAL_FLUSH_GFLUSH (0x00000001u)#define CSL_DSPMMU_GFLUSH_REG_RESETVAL   (0x00000000u)/** *  FLUSH_ENTRY_REG */#define CSL_DSPMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_MASK (0x00000001u)#define CSL_DSPMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_SHIFT (0x00000000u)#define CSL_DSPMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_RESETVAL (0x00000000u)#define CSL_DSPMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_FLUSHONEENTRY (0x00000001u)#define CSL_DSPMMU_FLUSH_ENTRY_REG_RESETVAL (0x00000000u)/** *  READ_CAM_H_REG */#define CSL_DSPMMU_READ_CAM_H_REG_VA_TAG_L1_H_MASK (0x00000003u)#define CSL_DSPMMU_READ_CAM_H_REG_VA_TAG_L1_H_SHIFT (0x00000000u)#define CSL_DSPMMU_READ_CAM_H_REG_VA_TAG_L1_H_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_CAM_H_REG_RESETVAL (0x00000000u)/** *  READ_CAM_L_REG */#define CSL_DSPMMU_READ_CAM_L_REG_VA_TAG_L1_L_MASK (0x0000C000u)#define CSL_DSPMMU_READ_CAM_L_REG_VA_TAG_L1_L_SHIFT (0x0000000Eu)#define CSL_DSPMMU_READ_CAM_L_REG_VA_TAG_L1_L_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_CAM_L_REG_VA_TAG_L2_MASK (0x00003FF0u)#define CSL_DSPMMU_READ_CAM_L_REG_VA_TAG_L2_SHIFT (0x00000004u)#define CSL_DSPMMU_READ_CAM_L_REG_VA_TAG_L2_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_CAM_L_REG_P_MASK (0x00000008u)#define CSL_DSPMMU_READ_CAM_L_REG_P_SHIFT (0x00000003u)#define CSL_DSPMMU_READ_CAM_L_REG_P_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_CAM_L_REG_V_MASK (0x00000004u)#define CSL_DSPMMU_READ_CAM_L_REG_V_SHIFT (0x00000002u)#define CSL_DSPMMU_READ_CAM_L_REG_V_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_CAM_L_REG_SLST_MASK (0x00000003u)#define CSL_DSPMMU_READ_CAM_L_REG_SLST_SHIFT (0x00000000u)#define CSL_DSPMMU_READ_CAM_L_REG_SLST_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_CAM_L_REG_RESETVAL (0x00000000u)/** *  READ_RAM_H_REG */#define CSL_DSPMMU_READ_RAM_H_REG_RAM_MSB_MASK (0x0000FFFFu)#define CSL_DSPMMU_READ_RAM_H_REG_RAM_MSB_SHIFT (0x00000000u)#define CSL_DSPMMU_READ_RAM_H_REG_RAM_MSB_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_RAM_H_REG_RESETVAL (0x00000000u)/** *  READ_RAM_L_REG */#define CSL_DSPMMU_READ_RAM_L_REG_RAM_LSB_MASK (0x0000FC00u)#define CSL_DSPMMU_READ_RAM_L_REG_RAM_LSB_SHIFT (0x0000000Au)#define CSL_DSPMMU_READ_RAM_L_REG_RAM_LSB_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_RAM_L_REG_AP_MASK     (0x00000300u)#define CSL_DSPMMU_READ_RAM_L_REG_AP_SHIFT    (0x00000008u)#define CSL_DSPMMU_READ_RAM_L_REG_AP_RESETVAL (0x00000000u)#define CSL_DSPMMU_READ_RAM_L_REG_RESETVAL (0x00000000u)/** *  DSPMMU_IDLE_CTRL */#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_GL_PDE_MASK (0x00000002u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_GL_PDE_SHIFT (0x00000001u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_GL_PDE_RESETVAL (0x00000000u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_GL_PDE_NORMAL (0x00000000u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_GL_PDE_POWERDOWN (0x00000001u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_AUTOGATING_EN_MASK (0x00000001u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_AUTOGATING_EN_SHIFT (0x00000000u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_AUTOGATING_EN_RESETVAL (0x00000000u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_AUTOGATING_EN_DISABLE (0x00000000u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_AUTOGATING_EN_ENABLE (0x00000001u)#define CSL_DSPMMU_DSPMMU_IDLE_CTRL_RESETVAL (0x00000000u)#endif

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