cslr_dma.h

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#ifndef _CSLR_DMA_001_H_
#define _CSLR_DMA_001_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated.
 * All Rights Reserved
 *********************************************************************/
 /** \file cslr_dma_001.h
 *
 * \brief This file contains the Register Desciptions for DMA
 *	    Register definitions Comply with Omap3.2 spec.
 *
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure for CHA
\**************************************************************************/
typedef struct  {
    volatile Uint16 CSDP;
    volatile Uint16 CCR;
    volatile Uint16 CICR;
    volatile Uint16 CSR;
    volatile Uint16 CSSAL;
    volatile Uint16 CSSAU;
    volatile Uint16 CDSAL;
    volatile Uint16 CDSAU;
    volatile Uint16 CEN;
    volatile Uint16 CFN;
    volatile Uint16 CSFI;
    volatile Uint16 CSEI;
    volatile Uint16 CSAC;
    volatile Uint16 CDAC;
    volatile Uint16 CDEI;
    volatile Uint16 CDFI;
    volatile Uint16 COLORL;
    volatile Uint16 COLORU;
    volatile Uint16 CCR2;
    volatile Uint8 RSVD0[2];
    volatile Uint16 CLNKCTRL;
    volatile Uint16 LCHCTRL;
    volatile Uint8 RSVD1[20];
} CSL_DmaChaRegs;

/**************************************************************************\
* Register Overlay Structure for Gbl
\**************************************************************************/
typedef struct  {
    volatile Uint16 GCR;
    volatile Uint8 RSVD0[2];
    volatile Uint16 GSCR;
    volatile Uint8 RSVD1[2];
    volatile Uint16 GRST;
    volatile Uint8 RSVD2[56];
    volatile Uint16 HWID;
    volatile Uint16 PCHPID;
    volatile Uint16 PCHM0ID;
    volatile Uint16 PCHM1ID;
    volatile Uint16 PCHGID;
    volatile Uint16 PCHDID;
    volatile Uint16 CAPS0U;
    volatile Uint16 CAPS0L;
    volatile Uint16 CAPS1U;
    volatile Uint16 CAPS1L;
    volatile Uint16 CAPS2;
    volatile Uint16 CAPS3;
    volatile Uint16 CAPS4;
    volatile Uint8 RSVD3[4];
    volatile Uint16 PCHSRP0;
    volatile Uint8 RSVD4[30];
    volatile Uint16 PCHSRM0;
    volatile Uint16 PCHSRM1;
    volatile Uint8 RSVD5[60];
    volatile Uint16 PCHSRD0;
} CSL_DmaGblRegs;

/**************************************************************************\
* Register Overlay Structure for LCDCHA
\**************************************************************************/
typedef struct  {
    volatile Uint8 RSVD0[192];
    volatile Uint16 LCDCSDP;
    volatile Uint16 LCDCCR;
    volatile Uint16 LCDCTRL;
    volatile Uint8 RSVD1[2];
    volatile Uint16 LCDTOPB1L;
    volatile Uint16 LCDTOPB1U;
    volatile Uint16 LCDBOTB1L;
    volatile Uint16 LCDBOTB1U;
    volatile Uint16 LCDTOPB2L;
    volatile Uint16 LCDTOPB2U;
    volatile Uint16 LCDBOTB2L;
    volatile Uint16 LCDBOTB2U;
    volatile Uint16 LCDSRCEIB1;
    volatile Uint16 LCDSRCFIB1L;
    volatile Uint16 LCDSRCEIB2;
    volatile Uint16 LCDSRCFIB2L;
    volatile Uint16 LCDSRCENB1;
    volatile Uint16 LCDSRCENB2;
    volatile Uint16 LCDSRCFNB1;
    volatile Uint16 LCDSRCFNB2;
    volatile Uint8 RSVD2[2];
    volatile Uint16 LCDLCHCTRL;
    volatile Uint8 RSVD3[8];
    volatile Uint16 LCDSRCFIB1U;
    volatile Uint16 LCDSRCFIB2U;
} CSL_DmaLcdChaRegs;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    CSL_DmaChaRegs CHA[16];
    CSL_DmaGblRegs GLOBAL;
    volatile Uint8 RSVD0[1598];
    CSL_DmaLcdChaRegs LCDCHA;
} CSL_DmaRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
/** @brief Pointer to DMA Register Overlay Structure */
typedef volatile CSL_DmaRegs      * CSL_DmaRegsOvly;

/** @brief Pointer to DMA Global Register Overlay Structure */
typedef volatile CSL_DmaGblRegs   * CSL_DmaGlobalRegsOvly;

/** @brief Pointer to DMA Channel Register Overlay Structure */
typedef volatile CSL_DmaChaRegs   * CSL_DmaChaRegsOvly;

/** @brief Pointer to DMA Lcd Channel Register Overlay Structure */
typedef volatile CSL_DmaLcdChaRegs   * CSL_DmaLcdChaRegsOvly;


/**************************************************************************\
* Register Id's
\**************************************************************************/
typedef enum  {
   CSL_DMA_CSDP = 0x0000u,
   CSL_DMA_CCR = 0x0002u,
   CSL_DMA_CICR = 0x0004u,
   CSL_DMA_CSR = 0x0006u,
   CSL_DMA_CSSAL = 0x0008u,
   CSL_DMA_CSSAU = 0x000au,
   CSL_DMA_CDSAL = 0x000cu,
   CSL_DMA_CDSAU = 0x000eu,
   CSL_DMA_CEN = 0x0010u,
   CSL_DMA_CFN = 0x0012u,
   CSL_DMA_CSFI = 0x0014u,
   CSL_DMA_CSEI = 0x0016u,
   CSL_DMA_CSAC = 0x0018u,
   CSL_DMA_CDAC = 0x001au,
   CSL_DMA_CDEI = 0x001cu,
   CSL_DMA_CDFI = 0x001eu,
   CSL_DMA_COLORL = 0x0020u,
   CSL_DMA_COLORU = 0x0022u,
   CSL_DMA_CCR2 = 0x0024u,
   CSL_DMA_CLNKCTRL = 0x0028u,
   CSL_DMA_LCHCTRL = 0x002au,
   CSL_DMA_GCR = 0x0000u,
   CSL_DMA_GSCR = 0x0004u,
   CSL_DMA_GRST = 0x0008u,
   CSL_DMA_HWID = 0x0042u,
   CSL_DMA_PCHPID = 0x0044u,
   CSL_DMA_PCHM0ID = 0x0046u,
   CSL_DMA_PCHM1ID = 0x0048u,
   CSL_DMA_PCHGID = 0x004au,
   CSL_DMA_PCHDID = 0x004cu,
   CSL_DMA_CAPS0U = 0x004eu,
   CSL_DMA_CAPS0L = 0x0050u,
   CSL_DMA_CAPS1U = 0x0052u,
   CSL_DMA_CAPS1L = 0x0054u,
   CSL_DMA_CAPS2 = 0x0056u,
   CSL_DMA_CAPS3 = 0x0058u,
   CSL_DMA_CAPS4 = 0x005au,
   CSL_DMA_PCHSRP0 = 0x0060u,
   CSL_DMA_PCHSRM0 = 0x0080u,
   CSL_DMA_PCHSRM1 = 0x0082u,
   CSL_DMA_PCHSRD0 = 0x00c0u,
   CSL_DMA_LCDCSDP = 0x00c0u,
   CSL_DMA_LCDCCR = 0x00c2u,
   CSL_DMA_LCDCTRL = 0x00c4u,
   CSL_DMA_LCDTOPB1L = 0x00c8u,
   CSL_DMA_LCDTOPB1U = 0x00cau,
   CSL_DMA_LCDBOTB1L = 0x00ccu,
   CSL_DMA_LCDBOTB1U = 0x00ceu,
   CSL_DMA_LCDTOPB2L = 0x00d0u,
   CSL_DMA_LCDTOPB2U = 0x00d2u,
   CSL_DMA_LCDBOTB2L = 0x00d4u,
   CSL_DMA_LCDBOTB2U = 0x00d6u,
   CSL_DMA_LCDSRCEIB1 = 0x00d8u,
   CSL_DMA_LCDSRCFIB1L = 0x00dau,
   CSL_DMA_LCDSRCEIB2 = 0x00dcu,
   CSL_DMA_LCDSRCFIB2L = 0x00deu,
   CSL_DMA_LCDSRCENB1 = 0x00e0u,
   CSL_DMA_LCDSRCENB2 = 0x00e2u,
   CSL_DMA_LCDSRCFNB1 = 0x00e4u,
   CSL_DMA_LCDSRCFNB2 = 0x00e6u,
   CSL_DMA_LCDLCHCTRL = 0x00eau,
   CSL_DMA_LCDSRCFIB1U = 0x00f4u,
   CSL_DMA_LCDSRCFIB2U = 0x00f6u
} CSL_DmaRegIds;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* GCR */

#define CSL_DMA_GCR_ROUNDROBINDISABLE_MASK (0x00000010u)
#define CSL_DMA_GCR_ROUNDROBINDISABLE_SHIFT (0x00000004u)
#define CSL_DMA_GCR_ROUNDROBINDISABLE_RESETVAL (0x00000000u)

#define CSL_DMA_GCR_AUTOGATINGON_MASK    (0x00000008u)
#define CSL_DMA_GCR_AUTOGATINGON_SHIFT   (0x00000003u)
#define CSL_DMA_GCR_AUTOGATINGON_RESETVAL (0x00000001u)

#define CSL_DMA_GCR_FREE_MASK            (0x00000004u)
#define CSL_DMA_GCR_FREE_SHIFT           (0x00000002u)
#define CSL_DMA_GCR_FREE_RESETVAL        (0x00000000u)

#define CSL_DMA_GCR_RESETVAL             (0x00000008u)

/* GSCR */

#define CSL_DMA_GSCR_OMAP31MAPPINGDISABLE_MASK (0x00000008u)
#define CSL_DMA_GSCR_OMAP31MAPPINGDISABLE_SHIFT (0x00000003u)
#define CSL_DMA_GSCR_OMAP31MAPPINGDISABLE_RESETVAL (0x00000000u)

#define CSL_DMA_GSCR_RESETVAL            (0x00000000u)

/* GRST */

#define CSL_DMA_GRST_SWRESET_MASK        (0x00000001u)
#define CSL_DMA_GRST_SWRESET_SHIFT       (0x00000000u)
#define CSL_DMA_GRST_SWRESET_RESETVAL    (0x00000000u)

#define CSL_DMA_GRST_RESETVAL            (0x00000000u)

/* HWID */

#define CSL_DMA_HWID_HWID_MASK           (0x0000FFFFu)
#define CSL_DMA_HWID_HWID_SHIFT          (0x00000000u)
#define CSL_DMA_HWID_HWID_RESETVAL       (0x00000001u)

#define CSL_DMA_HWID_RESETVAL            (0x00000001u)

/* PCHPID */

#define CSL_DMA_PCHPID_PCHPID_MASK       (0x0000FFFFu)
#define CSL_DMA_PCHPID_PCHPID_SHIFT      (0x00000000u)
#define CSL_DMA_PCHPID_PCHPID_RESETVAL   (0x00000001u)

#define CSL_DMA_PCHPID_RESETVAL          (0x00000001u)

/* PCHM0ID */

#define CSL_DMA_PCHM0ID_PCHM0ID_MASK     (0x0000FFFFu)
#define CSL_DMA_PCHM0ID_PCHM0ID_SHIFT    (0x00000000u)
#define CSL_DMA_PCHM0ID_PCHM0ID_RESETVAL (0x00000001u)

#define CSL_DMA_PCHM0ID_RESETVAL         (0x00000001u)

/* PCHM1ID */

#define CSL_DMA_PCHM1ID_PCHM1ID_MASK     (0x0000FFFFu)
#define CSL_DMA_PCHM1ID_PCHM1ID_SHIFT    (0x00000000u)
#define CSL_DMA_PCHM1ID_PCHM1ID_RESETVAL (0x00000001u)

#define CSL_DMA_PCHM1ID_RESETVAL         (0x00000001u)

/* PCHGID */

#define CSL_DMA_PCHGID_PCHGID_MASK       (0x0000FFFFu)
#define CSL_DMA_PCHGID_PCHGID_SHIFT      (0x00000000u)
#define CSL_DMA_PCHGID_PCHGID_RESETVAL   (0x00000000u)

#define CSL_DMA_PCHGID_RESETVAL          (0x00000000u)

/* PCHDID */

#define CSL_DMA_PCHDID_PCHDID_MASK       (0x0000FFFFu)
#define CSL_DMA_PCHDID_PCHDID_SHIFT      (0x00000000u)
#define CSL_DMA_PCHDID_PCHDID_RESETVAL   (0x00000001u)

#define CSL_DMA_PCHDID_RESETVAL          (0x00000001u)

/* CAPS0U */

#define CSL_DMA_CAPS0U_CONSTFILLCAP_MASK (0x00000008u)
#define CSL_DMA_CAPS0U_CONSTFILLCAP_SHIFT (0x00000003u)
#define CSL_DMA_CAPS0U_CONSTFILLCAP_RESETVAL (0x00000001u)

#define CSL_DMA_CAPS0U_TRANSBLTCAP_MASK  (0x00000004u)
#define CSL_DMA_CAPS0U_TRANSBLTCAP_SHIFT (0x00000002u)
#define CSL_DMA_CAPS0U_TRANSBLTCAP_RESETVAL (0x00000001u)

#define CSL_DMA_CAPS0U_OVERLAPDETECTCAP_MASK (0x00000002u)
#define CSL_DMA_CAPS0U_OVERLAPDETECTCAP_SHIFT (0x00000001u)
#define CSL_DMA_CAPS0U_OVERLAPDETECTCAP_RESETVAL (0x00000000u)

#define CSL_DMA_CAPS0U_DIRECTIONALBLTCAP_MASK (0x00000001u)
#define CSL_DMA_CAPS0U_DIRECTIONALBLTCAP_SHIFT (0x00000000u)
#define CSL_DMA_CAPS0U_DIRECTIONALBLTCAP_RESETVAL (0x00000000u)

#define CSL_DMA_CAPS0U_RESETVAL          (0x0000000Cu)

/* CAPS0L */

#define CSL_DMA_CAPS0L_SUBBYTEDESTCAP_MASK (0x00000004u)
#define CSL_DMA_CAPS0L_SUBBYTEDESTCAP_SHIFT (0x00000002u)
#define CSL_DMA_CAPS0L_SUBBYTEDESTCAP_RESETVAL (0x00000000u)

#define CSL_DMA_CAPS0L_ORIGINCOORDCAP_MASK (0x00000001u)
#define CSL_DMA_CAPS0L_ORIGINCOORDCAP_SHIFT (0x00000000u)
#define CSL_DMA_CAPS0L_ORIGINCOORDCAP_RESETVAL (0x00000000u)

#define CSL_DMA_CAPS0L_RESETVAL          (0x00000000u)

/* CAPS1U */

#define CSL_DMA_CAPS1U_RESETVAL          (0x00000000u)

/* CAPS1L */

#define CSL_DMA_CAPS1L_1BITPALLETIZEDCAP_MASK (0x00000002u)
#define CSL_DMA_CAPS1L_1BITPALLETIZEDCAP_SHIFT (0x00000001u)
#define CSL_DMA_CAPS1L_1BITPALLETIZEDCAP_RESETVAL (0x00000000u)

#define CSL_DMA_CAPS1L_RESETVAL          (0x00000000u)

/* CAPS2 */

#define CSL_DMA_CAPS2_SEPARATEINDEXCAP_MASK (0x00000100u)
#define CSL_DMA_CAPS2_SEPARATEINDEXCAP_SHIFT (0x00000008u)
#define CSL_DMA_CAPS2_SEPARATEINDEXCAP_RESETVAL (0x00000001u)

#define CSL_DMA_CAPS2_DSTDBLINDEXCAP_MASK (0x00000080u)
#define CSL_DMA_CAPS2_DSTDBLINDEXCAP_SHIFT (0x00000007u)