cslr_cam.h

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/** ============================================================================
 *   @file  cslr_cam.h
 *
 *   @path  $(CSLPATH)\arm\cam\src
 *
 *   @desc  Register layer header file for the camera parallel interface CSL
 * =============================================================================
 */
 
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/* =============================================================================
 *  Revision History
 *  ================
 *  10-Aug-2004 ka File Created.
 *
 * =============================================================================
 */

#ifndef _CSLR_CAM_H_
#define _CSLR_CAM_H_

#include <cslr.h>
#include <tistdtypes.h>

/**
 * Register overlay structure
 */
typedef struct  {
    /** Clock control register */
    volatile Uint32 CTRLCLOCK;
    /** Interrupt source status register */
    volatile Uint32 IT_STATUS;
    /** Camera interface mode configuration register */
    volatile Uint32 MODE;
    /** Status register */
    volatile Uint32 STATUS;
    /** Image data register */
    volatile Uint32 CAMDATA;
    /** Camera interface GPIO register */
    volatile Uint32 GPIO;
    /** FIFO peak counter register */
    volatile Uint32 PEAK_COUNTER;
} CSL_CamRegs;

/**
 * Overlay structure typedef definition
 */
typedef volatile CSL_CamRegs * CSL_CamRegsOvly;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* CTRLCLOCK */

/** CTRLCLOCK LCLK_EN field mask */
#define CSL_CAM_CTRLCLOCK_LCLK_EN_MASK   (0x00000080u)
/** CTRLCLOCK LCLK_EN field shift */
#define CSL_CAM_CTRLCLOCK_LCLK_EN_SHIFT  (0x00000007u)
/** CTRLCLOCK LCLK_EN field reset value */
#define CSL_CAM_CTRLCLOCK_LCLK_EN_RESETVAL (0x00000000u)

/*----LCLK_EN Tokens----*/

/** CTRLCLOCK LCLK_EN - Disable CAM.LCLK */
#define CSL_CAM_CTRLCLOCK_LCLK_EN_DISABLE (0x00000000u)
/** CTRLCLOCK LCLK_EN - Enable CAM.LCLK */
#define CSL_CAM_CTRLCLOCK_LCLK_EN_ENABLE (0x00000001u)

/** CTRLCLOCK MCLK_EN field mask */
#define CSL_CAM_CTRLCLOCK_MCLK_EN_MASK   (0x00000020u)
/** CTRLCLOCK MCLK_EN field shift value */
#define CSL_CAM_CTRLCLOCK_MCLK_EN_SHIFT  (0x00000005u)
/** CTRLCLOCK MCLK_EN field reset value */
#define CSL_CAM_CTRLCLOCK_MCLK_EN_RESETVAL (0x00000000u)

/*----MCLK_EN Tokens----*/

/** CTRLCLOCK MCLK_EN - Disable internal clock of interface */
#define CSL_CAM_CTRLCLOCK_MCLK_EN_DISABLE (0x00000000u)
/** CTRLCLOCK MCLK_EN - Enable internal clock of interface */
#define CSL_CAM_CTRLCLOCK_MCLK_EN_ENABLE (0x00000001u)

/** CTRLCLOCK CAMEX_EN field mask */
#define CSL_CAM_CTRLCLOCK_CAMEXCLK_EN_MASK (0x00000010u)
/** CTRLCLOCK CAMEX_EN field shift value */
#define CSL_CAM_CTRLCLOCK_CAMEXCLK_EN_SHIFT (0x00000004u)
/** CTRLCLOCK CAMEX_EN field reset value */
#define CSL_CAM_CTRLCLOCK_CAMEXCLK_EN_RESETVAL (0x00000000u)

/*----CAMEXCLK_EN Tokens----*/

/** CTRLCLOCK MCLK_EN - Disable CAM.EXCLK */
#define CSL_CAM_CTRLCLOCK_CAMEXCLK_EN_DISABLE (0x00000000u)
/** CTRLCLOCK MCLK_EN - Enable CAM.EXCLK */
#define CSL_CAM_CTRLCLOCK_CAMEXCLK_EN_ENABLE (0x00000001u)

/** CTRLCLOCK POLCLK field mask value */
#define CSL_CAM_CTRLCLOCK_POLCLK_MASK    (0x00000008u)
/** CTRLCLOCK POLCLK field shift value */
#define CSL_CAM_CTRLCLOCK_POLCLK_SHIFT   (0x00000003u)
/** CTRLCLOCK POLCLK field reset value */
#define CSL_CAM_CTRLCLOCK_POLCLK_RESETVAL (0x00000000u)

/*----POLCLK Tokens----*/

/** CTRLCLOCK POLCLK - Configure rising edge as the active edge */
#define CSL_CAM_CTRLCLOCK_POLCLK_RISING_EDGE (0x00000000u)
/** CTRLCLOCK POLCLK - Configure falling edge as the active edge */
#define CSL_CAM_CTRLCLOCK_POLCLK_FALLING_EDGE (0x00000001u)

/** CTRLCLOCK FOSCMOD field mask value */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_MASK   (0x00000007u)
/** CTRLCLOCK FOSCMOD field shift value */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_SHIFT  (0x00000000u)
/** CTRLCLOCK FOSCMOD field reset value */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_RESETVAL (0x00000000u)

/*----ORDERCAMD Tokens----*/

/** Do not swap the recieved bytes */
#define CSL_CAM_MODE_ORDERCAMD_NOT_SWAPPED (0x00000000u)

/** Swap the recieved bytes */
#define CSL_CAM_MODE_ORDERCAMD_SWAPPED (0x00000001u)


/*----FOSCMOD Tokens----*/

/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 8 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_8 (0x00000000u)
/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 3 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_3 (0x00000001u)
/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 16 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_16 (0x00000002u)
/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 2 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_2 (0x00000003u)
/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 10 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_10 (0x00000004u)
/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 4 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_4 (0x00000005u)
/** CTRLCLOCK FOSCMOD  - Divide ARM_PER_CK by 12 */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_ARM_PER_CK_12 (0x00000006u)
/** CTRLCLOCK FOSCMOD  - Disables the CAM.EXCLK */
#define CSL_CAM_CTRLCLOCK_FOSCMOD_INACTIVE (0x00000007u)

/** CTRLCLOCK register reset value */
#define CSL_CAM_CTRLCLOCK_RESETVAL       (0x00000000u)

/* IT_STATUS */

/** IT_STATUS DATA_TRANSFER mask value */
#define CSL_CAM_IT_STATUS_DATA_TRANSFER_MASK (0x00000020u)
/** IT_STATUS DATA_TRANSFER field shift value */
#define CSL_CAM_IT_STATUS_DATA_TRANSFER_SHIFT (0x00000005u)
/** IT_STATUS DATA_TRANSFER field reset value */
#define CSL_CAM_IT_STATUS_DATA_TRANSFER_RESETVAL (0x00000000u)

/** IT_STATUS FIFO FULL mask value */
#define CSL_CAM_IT_STATUS_FIFO_FULL_MASK (0x00000010u)
/** IT_STATUS FIFO FULL field shift value */
#define CSL_CAM_IT_STATUS_FIFO_FULL_SHIFT (0x00000004u)
/** IT_STATUS FIFO FULL field reset value */
#define CSL_CAM_IT_STATUS_FIFO_FULL_RESETVAL (0x00000000u)

/** IT_STATUS H_DOWN field mask value */
#define CSL_CAM_IT_STATUS_H_DOWN_MASK    (0x00000008u)
/** IT_STATUS H_DOWN field shift value */
#define CSL_CAM_IT_STATUS_H_DOWN_SHIFT   (0x00000003u)
/** IT_STATUS H_DOWN field reset value */
#define CSL_CAM_IT_STATUS_H_DOWN_RESETVAL (0x00000000u)

/** IT_STATUS H_UP field mask value */
#define CSL_CAM_IT_STATUS_H_UP_MASK      (0x00000004u)
/** IT_STATUS H_UP field shift value */
#define CSL_CAM_IT_STATUS_H_UP_SHIFT     (0x00000002u)
/** IT_STATUS H_UP field reset value */
#define CSL_CAM_IT_STATUS_H_UP_RESETVAL  (0x00000000u)

/** IT_STATUS V_DOWN field mask value */
#define CSL_CAM_IT_STATUS_V_DOWN_MASK    (0x00000002u)
/** IT_STATUS V_DOWN field shift value */
#define CSL_CAM_IT_STATUS_V_DOWN_SHIFT   (0x00000001u)
/** IT_STATUS V_DOWN field reset value */
#define CSL_CAM_IT_STATUS_V_DOWN_RESETVAL (0x00000000u)

/** IT_STATUS V_UP field mask value */
#define CSL_CAM_IT_STATUS_V_UP_MASK      (0x00000001u)
/** IT_STATUS V_UP field shift value */
#define CSL_CAM_IT_STATUS_V_UP_SHIFT     (0x00000000u)
/** IT_STATUS V_UP field reset value */
#define CSL_CAM_IT_STATUS_V_UP_RESETVAL  (0x00000000u)

/** IT_STATUS V_UP reset value */
#define CSL_CAM_IT_STATUS_RESETVAL       (0x00000000u)

/* MODE */

/** MODE RAS_FIFO field mask value */
#define CSL_CAM_MODE_RAZ_FIFO_MASK       (0x00040000u)
/** MODE RAS_FIFO field shift value */
#define CSL_CAM_MODE_RAZ_FIFO_SHIFT      (0x00000012u)
/** MODE RAS_FIFO field reset value */
#define CSL_CAM_MODE_RAZ_FIFO_RESETVAL   (0x00000000u)

/** MODE EN_FIFO field mask value */
#define CSL_CAM_MODE_EN_FIFO_FULL_MASK   (0x00020000u)
/** MODE EN_FIFO field shift value */
#define CSL_CAM_MODE_EN_FIFO_FULL_SHIFT  (0x00000011u)
/** MODE EN_FIFO field reset value */
#define CSL_CAM_MODE_EN_FIFO_FULL_RESETVAL (0x00000000u)

/*----EN_FIFO_FULL Tokens----*/

/** MODE EN_FIFO_FULL - Disable interrupt on FIFO_FULL */
#define CSL_CAM_MODE_EN_FIFO_FULL_DISABLE (0x00000000u)
/** MODE EN_FIFO_FULL - Enable interrupt on FIFO_FULL */
#define CSL_CAM_MODE_EN_FIFO_FULL_ENABLE (0x00000001u)

/** MODE EN_NIRQ field mask value */
#define CSL_CAM_MODE_EN_NIRQ_MASK        (0x00010000u)
/** MODE EN_NIRQ field shift value */
#define CSL_CAM_MODE_EN_NIRQ_SHIFT       (0x00000010u)
/** MODE EN_NIRQ field reset value */
#define CSL_CAM_MODE_EN_NIRQ_RESETVAL    (0x00000000u)

/*----EN_NIRQ Tokens----*/

/** MODE EN_NIRQ - Disable data transfer interrupt */
#define CSL_CAM_MODE_EN_NIRQ_DISABLE     (0x00000000u)
/** MODE EN_NIRQ - Enable data transfer interrupt */
#define CSL_CAM_MODE_EN_NIRQ_ENABLE      (0x00000001u)

/** MODE THRESHOLD field mask value */
#define CSL_CAM_MODE_THRESHOLD_MASK      (0x0000FE00u)
/** MODE THRESHOLD field shift value */
#define CSL_CAM_MODE_THRESHOLD_SHIFT     (0x00000009u)
/** MODE THRESHOLD field reset value */
#define CSL_CAM_MODE_THRESHOLD_RESETVAL  (0x00000000u)

/** MODE DMA field mask value */
#define CSL_CAM_MODE_DMA_MASK            (0x00000100u)
/** MODE DMA field shift value */
#define CSL_CAM_MODE_DMA_SHIFT           (0x00000008u)
/** MODE DMA field reset value */
#define CSL_CAM_MODE_DMA_RESETVAL        (0x00000000u)

/** MODE EN_H_DOWN field mask value */
#define CSL_CAM_MODE_EN_H_DOWN_MASK      (0x00000080u)
/** MODE EN_H_DOWN field shift value */
#define CSL_CAM_MODE_EN_H_DOWN_SHIFT     (0x00000007u)
/** MODE EN_H_DOWN field reset value */
#define CSL_CAM_MODE_EN_H_DOWN_RESETVAL  (0x00000000u)

/** MODE EN_H_UP field mask value */
#define CSL_CAM_MODE_EN_H_UP_MASK        (0x00000040u)
/** MODE EN_H_UP field shift value */
#define CSL_CAM_MODE_EN_H_UP_SHIFT       (0x00000006u)
/** MODE EN_H_UP field reset value */
#define CSL_CAM_MODE_EN_H_UP_RESETVAL    (0x00000000u)

/** MODE EN_V_DOWN field mask value */
#define CSL_CAM_MODE_EN_V_DOWN_MASK      (0x00000020u)
/** MODE EN_V_DOWN field shift value */
#define CSL_CAM_MODE_EN_V_DOWN_SHIFT     (0x00000005u)
/** MODE EN_V_DOWN field reset value */
#define CSL_CAM_MODE_EN_V_DOWN_RESETVAL  (0x00000000u)

/** MODE EN_V_UP field mask value */
#define CSL_CAM_MODE_EN_V_UP_MASK        (0x00000010u)
/** MODE EN_V_UP field shift value */
#define CSL_CAM_MODE_EN_V_UP_SHIFT       (0x00000004u)
/** MODE EN_V_UP field reset value */
#define CSL_CAM_MODE_EN_V_UP_RESETVAL    (0x00000000u)

/** MODE ORDERCAMD field mask value */
#define CSL_CAM_MODE_ORDERCAMD_MASK      (0x00000008u)
/** MODE ORDERCAMD field shift value */
#define CSL_CAM_MODE_ORDERCAMD_SHIFT     (0x00000003u)
/** MODE ORDERCAMD field reset value */
#define CSL_CAM_MODE_ORDERCAMD_RESETVAL  (0x00000000u)

/** MODE IMGSIZE field mask value */
#define CSL_CAM_MODE_IMGSIZE_MASK        (0x00000006u)
/** MODE IMGSIZE field shift value */
#define CSL_CAM_MODE_IMGSIZE_SHIFT       (0x00000001u)
/** MODE IMGSIZE field reset value */
#define CSL_CAM_MODE_IMGSIZE_RESETVAL    (0x00000000u)

/*----IMGSIZE Tokens----*/

/** MODE IMGSIZE - CIF image */
#define CSL_CAM_MODE_IMGSIZE_CIF         (0x00000000u)
/** MODE IMGSIZE - QCIF image */
#define CSL_CAM_MODE_IMGSIZE_QCIF        (0x00000001u)
/** MODE IMGSIZE - VGA image */
#define CSL_CAM_MODE_IMGSIZE_VGA         (0x00000002u)
/** MODE IMGSIZE - QVGA image */
#define CSL_CAM_MODE_IMGSIZE_QVGA        (0x00000003u)

/** MODE CAMOSC field mask value */
#define CSL_CAM_MODE_CAMOSC_MASK         (0x00000001u)
/** MODE CAMOSC field shift value */
#define CSL_CAM_MODE_CAMOSC_SHIFT        (0x00000000u)
/** MODE CAMOSC field reset value */
#define CSL_CAM_MODE_CAMOSC_RESETVAL     (0x00000000u)

/*----CAMOSC Tokens----*/

/** MODE CAMOSC - Synchronous mode */
#define CSL_CAM_MODE_CAMOSC_SYNC_MODE    (0x00000000u)
/** MODE CAMOSC - Asynchronous mode */
#define CSL_CAM_MODE_CAMOSC_ASYNC_MODE   (0x00000001u)

/** MODE register reset value */
#define CSL_CAM_MODE_RESETVAL            (0x00000000u)

/* STATUS */

/** STATUS HSTATUS field mask value */
#define CSL_CAM_STATUS_HSTATUS_MASK      (0x00000002u)
/** STATUS HSTATUS field shift value */
#define CSL_CAM_STATUS_HSTATUS_SHIFT     (0x00000001u)
/** STATUS HSTATUS field reset value */
#define CSL_CAM_STATUS_HSTATUS_RESETVAL  (0x00000000u)

/** STATUS VSTATUS field mask value */
#define CSL_CAM_STATUS_VSTATUS_MASK      (0x00000001u)
/** STATUS VSTATUS field shift value */
#define CSL_CAM_STATUS_VSTATUS_SHIFT     (0x00000000u)
/** STATUS VSTATUS field shift value */
#define CSL_CAM_STATUS_VSTATUS_RESETVAL  (0x00000000u)

/** STATUS STATUS reset value */
#define CSL_CAM_STATUS_RESETVAL          (0x00000000u)

/* GPIO */

/** STATUS GPIO field mask value */
#define CSL_CAM_GPIO_CAM_RST_MASK        (0x00000001u)
/** STATUS GPIO field shift value */
#define CSL_CAM_GPIO_CAM_RST_SHIFT       (0x00000000u)
/** STATUS GPIO field reset value */
#define CSL_CAM_GPIO_CAM_RST_RESETVAL    (0x00000000u)

/** STATUS GPIO regsiter reset value */
#define CSL_CAM_GPIO_RESETVAL            (0x00000000u)

/* CAMDATA */

/** STATUS CAMDATA CAMDATA field mask value */
#define CSL_CAM_CAMDATA_CAMDATA_MASK     (0xFFFFFFFFu)
/** STATUS CAMDATA CAMDATA field shift value */
#define CSL_CAM_CAMDATA_CAMDATA_SHIFT    (0x00000000u)
/** STATUS CAMDATA CAMDATA field reset value */
#define CSL_CAM_CAMDATA_CAMDATA_RESETVAL (0x00000000u)

/** STATUS CAMDATA register reset value */
#define CSL_CAM_CAMDATA_RESETVAL         (0x00000000u)

/* PEAK_COUNTER */

/** PEAK_COUNTER PEAK_COUNTER field mask */
#define CSL_CAM_PEAK_COUNTER_PEAK_COUNTER_MASK (0x0000007Fu)
/** PEAK_COUNTER PEAK_COUNTER field shift value*/
#define CSL_CAM_PEAK_COUNTER_PEAK_COUNTER_SHIFT (0x00000000u)
/** PEAK_COUNTER PEAK_COUNTER field reset value*/
#define CSL_CAM_PEAK_COUNTER_PEAK_COUNTER_RESETVAL (0x00000000u)

/** PEAK_COUNTER register field reset value */
#define CSL_CAM_PEAK_COUNTER_RESETVAL    (0x00000000u)

#endif