cslr_adcc.h

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#ifndef _CSLR_ADCC_001_H_#define _CSLR_ADCC_001_H_/********************************************************************* * Copyright (C) 2003-2004 Texas Instruments Incorporated.  * All Rights Reserved  *********************************************************************/ /** \file cslr_adcc_001.h *  * \brief This file contains the Register Desciptions for ADCC *  *********************************************************************/#include <cslr.h>#include <tistdtypes.h>/* the "expression" macros */#define SWAP_IO(val)           (val)#define SWAP_DATA(val)           (val)#define CSL_FMK32                CSL_FMK#define CSL_FEXT32               CSL_FEXT#define CSL_FINS32               CSL_FINS#define CSL_FMKT32               CSL_FMKT#define CSL_FINST32              CSL_FINST#define CSL_FMKR32               CSL_FMKR#define CSL_FEXTR32              CSL_FEXTR#define CSL_FINSR32              CSL_FINSR#define CSL_FINS32B              CSL_FINS/* Register Read/Write Macros */#define CSL_READ32(reg)                                                     \    (reg) #define CSL_WRITE32(reg, val)                                               \    ((reg) = (val))/**************************************************************************\* Register Overlay Structure for CHSET \**************************************************************************/typedef struct  {    volatile Uint32 CCR;    volatile Uint32 CT[4];    volatile Uint8 RSVD[12];} CSL_AdccChsetRegs;/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    volatile Uint32 PID;    volatile Uint32 GCR;    volatile Uint32 GCMD;    volatile Uint32 GSR;    volatile Uint32 ADC0CR;    volatile Uint32 ADC1CR;    volatile Uint8 RSVD0[8];    volatile Uint32 EOCCR;    volatile Uint8 RSVD1[12];    volatile Uint32 SGCR[2];    volatile Uint8 RSVD2[8];    volatile Uint32 FIFOCR;    volatile Uint32 FIFOSR;    volatile Uint8 RSVD3[8];    volatile Uint32 GTEQ0;    volatile Uint32 GTEQ1;    volatile Uint8 RSVD4[8];    volatile Uint32 IER0;    volatile Uint32 IER1;    volatile Uint32 IER2;    volatile Uint8 RSVD5[4];    volatile Uint32 ISR0;    volatile Uint32 ISR1;    volatile Uint32 ISR2;    volatile Uint8 RSVD6[4];    volatile Uint32 ICR0;    volatile Uint32 ICR1;    volatile Uint32 ICR2;    volatile Uint8 RSVD7[116];    volatile Uint16 CHSMP[17];    volatile Uint8 RSVD8[222];    CSL_AdccChsetRegs CHSET[17];} CSL_AdccRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/  typedef volatile CSL_AdccRegs *   CSL_AdccRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************//* PID */#define CSL_ADCC_PID_TYPE_MASK           (0x00FF0000u)#define CSL_ADCC_PID_TYPE_SHIFT          (0x00000010u)#define CSL_ADCC_PID_TYPE_RESETVAL       (0x00000001u)#define CSL_ADCC_PID_CLASS_MASK          (0x0000FF00u)#define CSL_ADCC_PID_CLASS_SHIFT         (0x00000008u)#define CSL_ADCC_PID_CLASS_RESETVAL      (0x0000000Cu)#define CSL_ADCC_PID_REV_MASK            (0x000000FFu)#define CSL_ADCC_PID_REV_SHIFT           (0x00000000u)#define CSL_ADCC_PID_REV_RESETVAL        (0x00000001u)#define CSL_ADCC_PID_RESETVAL            (0x00010C01u)/* GCR */#define CSL_ADCC_GCR_PDIV_MASK           (0x000F0000u)#define CSL_ADCC_GCR_PDIV_SHIFT          (0x00000010u)#define CSL_ADCC_GCR_PDIV_RESETVAL       (0x00000000u)#define CSL_ADCC_GCR_ENACH1DMA_MASK      (0x00008000u)#define CSL_ADCC_GCR_ENACH1DMA_SHIFT     (0x0000000Fu)#define CSL_ADCC_GCR_ENACH1DMA_RESETVAL  (0x00000000u)/*----ENACH1DMA Tokens----*/#define CSL_ADCC_GCR_ENACH1DMA_DISABLE   (0x00000000u)#define CSL_ADCC_GCR_ENACH1DMA_ENABLE    (0x00000001u)#define CSL_ADCC_GCR_ENACH0DMA_MASK      (0x00004000u)#define CSL_ADCC_GCR_ENACH0DMA_SHIFT     (0x0000000Eu)#define CSL_ADCC_GCR_ENACH0DMA_RESETVAL  (0x00000000u)/*----ENACH0DMA Tokens----*/#define CSL_ADCC_GCR_ENACH0DMA_DISABLE   (0x00000000u)#define CSL_ADCC_GCR_ENACH0DMA_ENABLE    (0x00000001u)#define CSL_ADCC_GCR_ENASG1DMA_MASK      (0x00002000u)#define CSL_ADCC_GCR_ENASG1DMA_SHIFT     (0x0000000Du)#define CSL_ADCC_GCR_ENASG1DMA_RESETVAL  (0x00000000u)/*----ENASG1DMA Tokens----*/#define CSL_ADCC_GCR_ENASG1DMA_DISABLE   (0x00000000u)#define CSL_ADCC_GCR_ENASG1DMA_ENABLE    (0x00000001u)#define CSL_ADCC_GCR_ENASG0DMA_MASK      (0x00001000u)#define CSL_ADCC_GCR_ENASG0DMA_SHIFT     (0x0000000Cu)#define CSL_ADCC_GCR_ENASG0DMA_RESETVAL  (0x00000000u)/*----ENASG0DMA Tokens----*/#define CSL_ADCC_GCR_ENASG0DMA_DISABLE   (0x00000000u)#define CSL_ADCC_GCR_ENASG0DMA_ENABLE    (0x00000001u)#define CSL_ADCC_GCR_ENASG1_MASK         (0x00000200u)#define CSL_ADCC_GCR_ENASG1_SHIFT        (0x00000009u)#define CSL_ADCC_GCR_ENASG1_RESETVAL     (0x00000000u)/*----ENASG1 Tokens----*/#define CSL_ADCC_GCR_ENASG1_DISABLE      (0x00000000u)#define CSL_ADCC_GCR_ENASG1_ENABLE       (0x00000001u)#define CSL_ADCC_GCR_ENASG0_MASK         (0x00000100u)#define CSL_ADCC_GCR_ENASG0_SHIFT        (0x00000008u)#define CSL_ADCC_GCR_ENASG0_RESETVAL     (0x00000000u)/*----ENASG0 Tokens----*/#define CSL_ADCC_GCR_ENASG0_DISABLE      (0x00000000u)#define CSL_ADCC_GCR_ENASG0_ENABLE       (0x00000001u)#define CSL_ADCC_GCR_ENAADC1_MASK        (0x00000020u)#define CSL_ADCC_GCR_ENAADC1_SHIFT       (0x00000005u)#define CSL_ADCC_GCR_ENAADC1_RESETVAL    (0x00000000u)/*----ENAADC1 Tokens----*/#define CSL_ADCC_GCR_ENAADC1_DISABLE     (0x00000000u)#define CSL_ADCC_GCR_ENAADC1_ENABLE      (0x00000001u)#define CSL_ADCC_GCR_ENAADC0_MASK        (0x00000010u)#define CSL_ADCC_GCR_ENAADC0_SHIFT       (0x00000004u)#define CSL_ADCC_GCR_ENAADC0_RESETVAL    (0x00000000u)/*----ENAADC0 Tokens----*/#define CSL_ADCC_GCR_ENAADC0_DISABLE     (0x00000000u)#define CSL_ADCC_GCR_ENAADC0_ENABLE      (0x00000001u)#define CSL_ADCC_GCR_ENAADCC_MASK        (0x00000001u)#define CSL_ADCC_GCR_ENAADCC_SHIFT       (0x00000000u)#define CSL_ADCC_GCR_ENAADCC_RESETVAL    (0x00000000u)/*----ENAADCC Tokens----*/#define CSL_ADCC_GCR_ENAADCC_DISABLE     (0x00000000u)#define CSL_ADCC_GCR_ENAADCC_ENABLE      (0x00000001u)#define CSL_ADCC_GCR_RESETVAL            (0x00000000u)/* GCMD */#define CSL_ADCC_GCMD_SSHOTCMD_MASK      (0x00000004u)#define CSL_ADCC_GCMD_SSHOTCMD_SHIFT     (0x00000002u)#define CSL_ADCC_GCMD_SSHOTCMD_RESETVAL  (0x00000000u)/*----SSHOTCMD Tokens----*/#define CSL_ADCC_GCMD_SSHOTCMD_START     (0x00000001u)#define CSL_ADCC_GCMD_SREADCMD_MASK      (0x00000002u)#define CSL_ADCC_GCMD_SREADCMD_SHIFT     (0x00000001u)#define CSL_ADCC_GCMD_SREADCMD_RESETVAL  (0x00000000u)/*----SREADCMD Tokens----*/#define CSL_ADCC_GCMD_SREADCMD_START     (0x00000001u)#define CSL_ADCC_GCMD_CMDEN_MASK         (0x00000001u)#define CSL_ADCC_GCMD_CMDEN_SHIFT        (0x00000000u)#define CSL_ADCC_GCMD_CMDEN_RESETVAL     (0x00000000u)/*----CMDEN Tokens----*/#define CSL_ADCC_GCMD_CMDEN_DISABLE      (0x00000000u)#define CSL_ADCC_GCMD_CMDEN_ENABLE       (0x00000001u)#define CSL_ADCC_GCMD_RESETVAL           (0x00000000u)/* GSR */#define CSL_ADCC_GSR_CH1DMAREQ_MASK      (0x00008000u)#define CSL_ADCC_GSR_CH1DMAREQ_SHIFT     (0x0000000Fu)#define CSL_ADCC_GSR_CH1DMAREQ_RESETVAL  (0x00000000u)/*----CH1DMAREQ Tokens----*/#define CSL_ADCC_GSR_CH1DMAREQ_INACTIVE  (0x00000000u)#define CSL_ADCC_GSR_CH1DMAREQ_ACTIVE    (0x00000001u)#define CSL_ADCC_GSR_CH0DMAREQ_MASK      (0x00004000u)#define CSL_ADCC_GSR_CH0DMAREQ_SHIFT     (0x0000000Eu)#define CSL_ADCC_GSR_CH0DMAREQ_RESETVAL  (0x00000000u)/*----CH0DMAREQ Tokens----*/#define CSL_ADCC_GSR_CH0DMAREQ_INACTIVE  (0x00000000u)#define CSL_ADCC_GSR_CH0DMAREQ_ACTIVE    (0x00000001u)#define CSL_ADCC_GSR_SG1DMAREQ_MASK      (0x00002000u)#define CSL_ADCC_GSR_SG1DMAREQ_SHIFT     (0x0000000Du)#define CSL_ADCC_GSR_SG1DMAREQ_RESETVAL  (0x00000000u)/*----SG1DMAREQ Tokens----*/#define CSL_ADCC_GSR_SG1DMAREQ_INACTIVE  (0x00000000u)#define CSL_ADCC_GSR_SG1DMAREQ_ACTIVE    (0x00000001u)#define CSL_ADCC_GSR_SG0DMAREQ_MASK      (0x00001000u)#define CSL_ADCC_GSR_SG0DMAREQ_SHIFT     (0x0000000Cu)#define CSL_ADCC_GSR_SG0DMAREQ_RESETVAL  (0x00000000u)/*----SG0DMAREQ Tokens----*/#define CSL_ADCC_GSR_SG0DMAREQ_INACTIVE  (0x00000000u)#define CSL_ADCC_GSR_SG0DMAREQ_ACTIVE    (0x00000001u)#define CSL_ADCC_GSR_SG1INPROG_MASK      (0x00000200u)#define CSL_ADCC_GSR_SG1INPROG_SHIFT     (0x00000009u)#define CSL_ADCC_GSR_SG1INPROG_RESETVAL  (0x00000000u)/*----SG1INPROG Tokens----*/#define CSL_ADCC_GSR_SG1INPROG_INACTIVE  (0x00000000u)#define CSL_ADCC_GSR_SG1INPROG_ACTIVE    (0x00000001u)#define CSL_ADCC_GSR_SG0INPROG_MASK      (0x00000100u)#define CSL_ADCC_GSR_SG0INPROG_SHIFT     (0x00000008u)#define CSL_ADCC_GSR_SG0INPROG_RESETVAL  (0x00000000u)/*----SG0INPROG Tokens----*/#define CSL_ADCC_GSR_SG0INPROG_INACTIVE  (0x00000000u)#define CSL_ADCC_GSR_SG0INPROG_ACTIVE    (0x00000001u)#define CSL_ADCC_GSR_ADC0RDY_MASK        (0x00000010u)#define CSL_ADCC_GSR_ADC0RDY_SHIFT       (0x00000004u)#define CSL_ADCC_GSR_ADC0RDY_RESETVAL    (0x00000000u)/*----ADC0RDY Tokens----*/#define CSL_ADCC_GSR_ADC0RDY_INACTIVE    (0x00000000u)#define CSL_ADCC_GSR_ADC0RDY_ACTIVE      (0x00000001u)#define CSL_ADCC_GSR_SSHOTINPROG_MASK    (0x00000004u)#define CSL_ADCC_GSR_SSHOTINPROG_SHIFT   (0x00000002u)#define CSL_ADCC_GSR_SSHOTINPROG_RESETVAL (0x00000000u)/*----SSHOTINPROG Tokens----*/#define CSL_ADCC_GSR_SSHOTINPROG_INACTIVE (0x00000000u)#define CSL_ADCC_GSR_SSHOTINPROG_ACTIVE  (0x00000001u)#define CSL_ADCC_GSR_SREADINPROG_MASK    (0x00000002u)#define CSL_ADCC_GSR_SREADINPROG_SHIFT   (0x00000001u)#define CSL_ADCC_GSR_SREADINPROG_RESETVAL (0x00000000u)/*----SREADINPROG Tokens----*/#define CSL_ADCC_GSR_SREADINPROG_INACTIVE (0x00000000u)#define CSL_ADCC_GSR_SREADINPROG_ACTIVE  (0x00000001u)#define CSL_ADCC_GSR_ADCCRDY_MASK        (0x00000001u)#define CSL_ADCC_GSR_ADCCRDY_SHIFT       (0x00000000u)#define CSL_ADCC_GSR_ADCCRDY_RESETVAL    (0x00000000u)/*----ADCCRDY Tokens----*/#define CSL_ADCC_GSR_ADCCRDY_INACTIVE    (0x00000000u)#define CSL_ADCC_GSR_ADCCRDY_ACTIVE      (0x00000001u)#define CSL_ADCC_GSR_RESETVAL            (0x00000000u)/* ADC0CR */#define CSL_ADCC_ADC0CR_ADC0DW_MASK      (0x00000F00u)#define CSL_ADCC_ADC0CR_ADC0DW_SHIFT     (0x00000008u)#define CSL_ADCC_ADC0CR_ADC0DW_RESETVAL  (0x00000007u)#define CSL_ADCC_ADC0CR_ADC0SCLK_MASK    (0x0000000Fu)#define CSL_ADCC_ADC0CR_ADC0SCLK_SHIFT   (0x00000000u)#define CSL_ADCC_ADC0CR_ADC0SCLK_RESETVAL (0x00000000u)#define CSL_ADCC_ADC0CR_RESETVAL         (0x00000700u)/* ADC1CR */#define CSL_ADCC_ADC1CR_CONT_CLK_MASK    (0x80000000u)#define CSL_ADCC_ADC1CR_CONT_CLK_SHIFT   (0x0000001Fu)#define CSL_ADCC_ADC1CR_CONT_CLK_RESETVAL (0x00000000u)/*----CONT_CLK Tokens----*/#define CSL_ADCC_ADC1CR_CONT_CLK_DISABLE (0x00000000u)#define CSL_ADCC_ADC1CR_CONT_CLK_ENABLE  (0x00000001u)#define CSL_ADCC_ADC1CR_HIZ_MASK         (0x40000000u)#define CSL_ADCC_ADC1CR_HIZ_SHIFT        (0x0000001Eu)#define CSL_ADCC_ADC1CR_HIZ_RESETVAL     (0x00000000u)/*----HIZ Tokens----*/#define CSL_ADCC_ADC1CR_HIZ_FUNCTIONAL   (0x00000000u)#define CSL_ADCC_ADC1CR_HIZ_TRI_STATE    (0x00000001u)#define CSL_ADCC_ADC1CR_CP_MASK          (0x20000000u)#define CSL_ADCC_ADC1CR_CP_SHIFT         (0x0000001Du)#define CSL_ADCC_ADC1CR_CP_RESETVAL      (0x00000000u)/*----CP Tokens----*/#define CSL_ADCC_ADC1CR_CP_MIDDLE        (0x00000000u)#define CSL_ADCC_ADC1CR_CP_BEGINING      (0x00000001u)#define CSL_ADCC_ADC1CR_CE_MASK          (0x10000000u)#define CSL_ADCC_ADC1CR_CE_SHIFT         (0x0000001Cu)#define CSL_ADCC_ADC1CR_CE_RESETVAL      (0x00000000u)/*----CE Tokens----*/#define CSL_ADCC_ADC1CR_CE_LOW           (0x00000000u)#define CSL_ADCC_ADC1CR_CE_HIGH          (0x00000001u)#define CSL_ADCC_ADC1CR_CI_MASK          (0x08000000u)#define CSL_ADCC_ADC1CR_CI_SHIFT         (0x0000001Bu)#define CSL_ADCC_ADC1CR_CI_RESETVAL      (0x00000000u)/*----CI Tokens----*/
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